An Efficient Design of Variable Length Decoder for MPEG-1/2/4

In this paper, we present an efficient look-up table (LUT)-based approach to design multipliers for GF(2 m ) generated by irreducible trinomials. A straightforward LUT-based multiplication requires a table of size (m×2 m ) bits for the Galois field of degree m. The LUT size, therefore, becomes quite large for the fields of large degrees recommended by the National Institute of Standards and Technology (NIST). Keeping that in view, we have proposed a digit-serial LUT-based design, where operand bits are grouped into digits of fixed width, and multiplication is performed in serial/parallel manner. We restrict the digit size to 4 to store only 16 words in the LUT to have lower area-delay complexity. We have also proposed a digit-parallel LUT-based design for high-speed applications, using the same LUT as the digit-serial design, at the cost of some additional multiplexors and combinational logic for parallel modular reductions and additions. We have presented a simple circuit for the initialization of LUT content, which can be used to update the LUT in three cycles whenever required. The proposed digit-serial design involves less area-complexity and less time-complexity than those of the existing LUT-based designs. The proposed digit-parallel design offers nearly 28 % improvement in area-delay product over the best of the existing LUT-based designs. NIST has recommended five binary finite fields for elliptic curve cryptography, out of which two are generated by the trinomials Q(x)=x 233+x 74+1 and Q(x)=x 409+x 87+1. In this paper, we have designed a reconfigurable multiplier that can be used for both these fields. The proposed reconfigurable multiplier is shown to have a negligible reconfiguration overhead and would be useful for cryptographic applications.

This paper presents an area and power-efficient architecture for serial commutator real-valued fast Fourier transform (FFT) using recursive look-up table (LUT). FFT computation consists of butterfly operations and twiddles factor multiplications. The area and power performance of FFT architectures are mainly limited by the multipliers. To address this, a new multiplier is proposed which stores the partial products in LUT. Moreover, by adding the shifted version of twiddle coefficients, the stored partial products gain symmetry, and thus the size of LUT can be reduced to half. Further symmetry is achieved by adding another shifted version of twiddle coefficients and so on. This makes the proposed LUT multiplier recursive in nature. A new data management scheme is suggested for the proposed architecture. To validate the proposed architecture, application-specific integrated circuit (ASIC) synthesis and field-programmable gate array (FPGA) implementation are carried out for different symmetry factor. For instance, the proposed architecture for 1024-point with symmetry factor of two achieves 39.11% less area, 42.29% less power, 33.27% less sliced LUT (SLUT) and 29.18% less flip-flop (FF) as compared to the best existing design.

This study presents the detailed design and analysis of a new memristor-based look-up table (LUT) for field programmable gate arrays (FPGAs). The proposed memory utilises memristors as storage elements with N-type metal-oxide-semiconductor transistors for row access. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation. The proposed method requires a RESTORE pulse only for the READ 0 operation. Moreover, the WRITE operation of the proposed method requires three power lines and a RESTORE pulse only for the READ 0 operation, thus saving 25% READ time when compared with previous methods. In addition, the proposed method does not require the REFRESH pulse and does not dissipate power during stand-by mode. Extensive simulation results are presented with respect to different operational features such as normalised state parameter, pulse width and LUT size. In addition to a circuit-level evaluation, the proposed LUT scheme has also been assessed with respect to FPGA implementation. Simulation results using sequential benchmarks mapped on Spartan 4 and 5 FPGAs show that the proposed non-volatile LUT outperforms existing static random access memory cell-based LUTs in terms of performance.

Computing with memory, which stores function responses of some input patterns into lookup tables offline and retrieves their values when encountering similar patterns (instead of performing online calculation), is a promising energy-efficient computing technique. No doubt to say, with a given lookup table size, the efficiency of this technique depends on which function responses are stored and how they are organized. In this paper, we propose a novel adaptive approximate lookup table based accelerator, wherein we store function responses in a hierarchical manner with increasing fine-grained granularity and accuracy. In addition, the proposed accelerator provides lightweight compensation on output results at different precision levels according to input patterns and output quality requirements. Moreover, our accelerator conducts adaptive lookup table search by exploiting input locality. Experimental results on various computation kernels show significant energy savings of the proposed accelerator over prior solutions.

A memory and speed efficient CAVLC (context adaptive variable length coding) decoder for H.264/AVC baseline profile is proposed. Because the CAVLC consists of a kind of bit-level operations, general processor (like RISC or MIPS) and DSP incorporating multiple parallel arithmetic units (like SIMD or VLIW) are ineffective to decode it. Though the dedicated hardwires are very effective to decode the CAVLC, they are expensive and not programmable. Also, the size of the CAVLC lookup table is more than 400 bytes. Demand for highly flexible and fast implementations and lower memory size for CAVLC decoding is rising nowadays. The four instructions--ShowBits, GetBits, FlushBits and LeadingBits, are designed after the exploiting of the functions coverage. In order to reduce the codewords matching miss and the lookup table size, a new grouping, remainder generation method and a merged lookup table (LUT) are used; and the specific group decoding instruction GroupDecoding is also presented. In summary, a based instruction set level acceleration with the codewords group partition hardware architecture is proposed to speed up the CAVLC decoding. Based on those instructions and the hardware platform, the CAVLC decoding can be significantly accelerated compared with the method in H.264 reference software. Simulation results show that the architecture is sufficient for the CAVLC decoding of 30 frames HDTV (1902 x 1080 pixels) per second.

This report presents results on the development of an adaptive predistorter for a generic TDMA transmitter A heterodyne architecture was used with the quadrature modulator and demodulator implemented as digital circuits. Previously reported results have indicated that increasing the look-up table (LUT) size improves the ACPR. Our results showed an opposite trend. Typical adjacent channel power rejection (ACPR) values of -57 dB were achieved using a 16 point LUT. The small LUT size may be attributed to memory effects inherent in a heterodyne system.

While the development of the optic interferometric sensors achieves great progress, one fact that restricts this development is the demodulation technique. An applicable demodulation method for interferometric sensors is called "The Phase Generated Carrier (PGC) demodulation". Yet this demodulation fails to content the large-scale sensors application for the limitations of the electronic devices. Another arctangent approach based on digital demodulator proves more advantages than the traditional Differentiate and Cross Multiply (DCM) approach which is used in PGC demodulation. In this paper, the arctangent approach based on PGC demodulation is discussed and simulated. Lookup table is used in the arctangent approach. Values equal to the existent data in the lookup table are chosen from the table, and values between two different data in the table are modulated to the linear approximate values. Two primary objects are aimed to demonstrate the advantages of the arctangent approach: (1). the noise analysis of this demodulation, considered two aspects: a. the relativity of the noise amplitude and the size of lookup table. Simulation result indicates that when double the lookup size, the noise amplitude decreases about 6dB; b. the influence to the noise generation which is leaded in by the rank of the polynomial approximate coefficients, the higher this rank is, the better the result comes. An approximate function is proposed about this relationship. (2). the measurement range, operation complexity, quality of operation, and applicability of the arctangent approach are discussed for an effective digital realization.

In the C-band high-speed long-reach optical intensity modulation direct detection (IM/DD) communication system, severe signal distortion, including chromatic dispersion and device bandwidth limitations, making the size of lookup tables (LUTs) required by equalizers too large to be operated. In this paper, we propose a cluster-assisting lookup table (CLUT) approach to reduce the table size significantly. In addition, we also propose multiplication-free CLUT-based decision-feedback equalizer (CLUT-DFE) and CLUT-based log-maximum a posteriori estimation with a fixed number of surviving states (CLUT-FS-MAP) to effectively compensate for channel distortions. Using the k-means clustering algorithm, the proposed CLUT significantly shortens the table size by reducing the number of independent variable values input. The table size of traditional LUTs increases exponentially with the filter tap number, making it impossible for LUTs to replace filters with tap numbers greater than 20. The CLUT breaks this limitation. The proposed schemes are experimentally performed in a C-band 61-Gb/s IM/DD optical on-off keying (OOK) system featuring a 3.65-GHz 3-dB bandwidth over a 100-km standard single mode fiber (SSMF). Compared to traditional LUT, CLUT reduces table size by about 10 orders of magnitude with the same performance. To the best of our knowledge, this study represents the first deployment of ultrasmall-size CLUT in equalization.

Recently, we have proposed the antisymmetric product coding (APC) and odd-multiple-storage (OMS) techniques for lookup-table (LUT) design for memory-based multipliers to be used in digital signal processing applications. Each of these techniques results in the reduction of the LUT size by a factor of two. In this brief, we present a different form of APC and a modified OMS scheme, in order to combine them for efficient memory-based multiplication. The proposed combined approach provides a reduction in LUT size to one-fourth of the conventional LUT. We have also suggested a simple technique for selective sign reversal to be used in the proposed design. It is shown that the proposed LUT design for small input sizes can be used for efficient implementation of high-precision multiplication by input operand decomposition. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD)-based multipliers. For 16- and 32-bit word sizes, respectively, it offers more than 30% and 50% of saving in area-delay product over the corresponding CSD multipliers.

A digital pre-distortion (DPD) scheme based on an adaptive-memory-length look-up table (AML-LUT) is proposed and experimentally demonstrated in a four-level pulse amplitude modulation (4-PAM) underwater optical wireless communication (UOWC) system. By implementing adaptive memory length for each pattern in the AML-LUT-based DPD, the size of the AML-LUT can be significantly reduced without sacrificing performance compared to both the full-size LUT and the multi-symbol simplified look-up table (MSS-LUT)-based DPDs. The performance of the proposed AML-LUT-based DPD is experimentally evaluated for a 625 Mbit/s 4-PAM UOWC over 1 m transmission length. Experimental results show that compared with the full-size LUT with a memory length of 7 (LUT-7)-based DPD, the proposed AML-LUT-based DPD (i) incurs a marginal power penalty of 0.5 dB at both the 7% hard-decision forward error correction (HD-FEC) and KP4-FEC threshold limits, while simultaneously reducing the implementation complexity (i.e., the LUT size) by 93%; (ii) achieves comparable transmission performance compared to the MSS-LUT-based DPD, while reducing the implementation complexity by 89%; and (iii) shows great potential for high-speed, low-complexity and memory-efficient intensity modulation and direct detection (IM/DD) UOWC and short-reach optical interconnects.

Logarithmic multiplier (LM) converts fixed-point (FxP) input operands to logarithmic numbers and performs multiplication with simple shift and addition operations, which achieves distinct power reduction, yet with significant single-sided errors. This paper proposes to fuse error compensation with logarithmic conversion by using customized look-up tables (LUTs). To avoid the use of large LUTs, partition strategies are designed for the optimization of LUTs. In addition, to effectively balance the accuracy and hardware costs, two iterative algorithms are proposed for generating precision-configurable LUTs. Based on the optimized LUTs, high-accuracy and low-power approximate LMs (LUT-ALMs) are constructed for 8-bit and 16-bit multiplications. Furthermore, to enhance the flexibility of data type and bit width, a mixed-mode LM (MM-ALM) supporting eight multiplication modes is devised. Compared with the exact 8-bit signed multiplier from Synopsys DesignWare (DW) library (DW-Exact), LUT-ALMs show up to 30.96% and 23.99% reductions in the power-delay product (PDP) and area-delay product (ADP), respectively, with a mean relative error distance (MRED) of 3.45%. Compared with state-of-the-art approximate 8- bit signed multipliers, LUT-ALMs form the Pareto front in terms of PDP and MRED. For 16-bit multiplication, LUT-ALMs obtain up to 70.90% and 62.13% savings in PDP and ADP with a MRED of 2.75%, compared with the corresponding DW-Exact. Compared with the corresponding mixed-mode exact multiplier constructed of DW multipliers, MM-ALM performing 8-bit multiplication achieves up to 57.44% and 47.99% reductions in PDP and ADP, respectively. When performing 4-bit multiplications, MM-ALM can save up to 37.16% savings in PDP. With lower hardware over-heads, LUT-ALMs and MM-ALM present comparable accuracy to the corresponding exact designs in the considered convolutional neural networks (CNNs) and image processing applications. The hardware description of the devised LMs is open-sourced at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://anonymous.4open.science/r/LUT-ALM-5FD1</uri>.

The computation capacity of conventional FPGAs is directly proportional to the size and expressive power of Look Up Table (LUT) resources. Individual LUT performance is limited by transistor switching time and power dissipation, defined by the CMOS fabrication process. In this paper we propose OLUT, an optical core implementation of LUT, which has the potential for low latency and low power computation. In addition, the use of Wavelength Division Multiplexing (WDM) allows parallel computation, which can further increase computation capacity. Preliminary experimental results demonstrate the potential for optically assisted on-chip computation.

Variable-length code (VLC) is the most popular data compression technique. Therefore, a high throughput variable-length decoder (VLD) is required in many applications. In this paper, we propose two simple modified methods which can increase throughput of memory-based two-bit structure variable-length decoder system. The additional hardware of the modified architecture is a control unit and some memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6 um CMOS process and MPEG2 coding table-15 can achieve 720 M bits/s with 100 MHz clock rate.

This paper presents a high-throughput variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS (255,239) code but also various shortened RS codes. Moreover, the variable-length architecture provides low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-nm CMOS standard cell technology, the proposed variable-length RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-Gbps data rate at clock frequency 300 MHz.

In this paper, we have implemented high performance FPGA based pipelined tree architectures for a combined unsigned and two's complement comparator, and an equality comparator which checks whether the sum of two numbers is equal to a third number. The comparator architectures deviate from the combined Look-Up Table (LUT) and carry chain based implementation which is inferred by the Xilinx Synthesis Tool. The feasibility of this work comes from the increased device density offered by the 6 and 7 series FPGA architectures from Xilinx, where every dual output function derived from a single LUT can be registered using a flip-flop present within the same slice as that of the LUT. Pipelining a tree based architecture completely eliminates the requirement of any synchronization registers for balancing the arrival time of the inputs and outputs, and their associated placement and routing challenges. The architecture has been realized through primitive instantiation of the logic elements to ensure packing of the dual output functions into a single LUT wherever possible, and the placement of the LUTs on the FPGA fabric using appropriate placement constraints. Implementation results clearly reveal the superiority of our design paradigm over behavioral style of modeling, where our proposed architectures consume less area, and operates at a higher speed in comparison to an identical circuit realized using behavioral descriptions.