A highly efficient substitution matrix loader for pairwise sequence alignment

Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned-memory, message-passing architecture of MARS. Three logic simulators-two multiple delay and one unit delay-have been implemented using slightly different configuration of the available PEs. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times that of an Amdahl 5870 system running a production-quality software simulator while retaining the accuracy of simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Field Programmable Gate Arrays (FPGAs) have proven their potential in accelerating High Performance Computing (HPC) Applications. Conventionally such accelerators predominantly use, FPGAs that contain fine-grained elements such as LookUp Tables (LUTs), Switch Blocks (SB) and Connection Blocks (CB) as basic programmable logic blocks.\nHowever, the conventional implementation suffers from high reconfiguration and development costs. In order to solve this problem, programmable logic components are defined at a virtual higher abstraction level. These components are called Processing Elements (PEs) and the group of PEs along with the inter-connection network form an architecture called a Virtual Coarse-Grained Reconfigurable Array (VCGRA). The abstraction helps to reconfigure the PEs faster at the intermediate level than at the lower-level of an FPGA.\nConventional VCGRA implementations (built on top of the lower levels of the FPGA) use functional resources such as LUTs to establish required connections (intra-connect) within a PE. In this paper, we propose to use the parameterized reconfiguration technique to implement the intra-connections of each PE with the aim to reduce the FPGA resource utilization (LUTs). The technique is used to parameterize the intra-connections with parameters that only change their value infrequently (whenever a new VCGRA function has to be reconfigured) and that are implemented as constants. Since the design is optimized for these constants at every moment in time, this reduces the resource utilization. Further, interconnections (network between the multiple PEs) of the VCGRA grid can also be parameterized so that both the inter- and intraconnect network of the VCGRA grid can be mapped onto the physical switch blocks of the FPGA. For every change in parameter values a specialized bitstream is generated on the fly and the FPGA is reconfigured using the parameterized run-time reconfiguration technique. Our results show a drastic reduction in FPGA LUT resource utilization in the PE by at least 30% and in the intra-network of the PE by 31% when implementing an HPC application.

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The "divide and conquer" technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(?V?1/2) for the processor arrays considered in this paper, where ?V? is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.

Massively parallel computers have been used for high performance computation in advanced science and technology. The Hypercube (HC) network: has attractive properties such as strong connectivity, recursive interconnection, simple routing, and a good link complexity. However, as the number of processing elements (PEs) increases, the diameter and average distance of HC become large in proportion to a logarithm of the number of PEs. This causes a large latency in communication between PEs and consequently, it reduces system performance. To solve this problem, two approaches have been investigated. The first approach is a theoretical approach to find a network topology reducing a diameter and an average distance between PEs. The second approach reduces the physical distances between PEs by integrating a large interconnection on a small chip for a silicon wafer. In this paper, we propose a new interconnection network; The HCQ (Horizontal Rotate Crossed Cube) by taking into account a WSI implementation, Theoretical network properties such as the diameter, the average distance, a routing algorithm are discussed in detail. It is shown that HCQ is a suitable network topology for massively parallel computers for WSI.

Cellular Genetic Algorithms (cGAs) exhibit a natural parallelism that makes them interesting candidates for hardware implementation, as several processing elements can operate simultaneously on subpopulations shared among them. This paper presents a scalable architecture for a cGA, suitable for FPGA implementation. A regular array of custom designed processing elements (PEs) works on a population of solutions that is spread into dual-port memory blocks locally shared by adjacent PEs. A travelling salesman problem with 150 cities was used to verify the implementation of the proposed cGA on a Virtex-6 FPGA, using a population of 128 solutions with different levels of parallelism (1, 4, 16 and 64 PEs). Results have shown that an increase of the number of PEs does not degrade the quality of the convergence of the iterative process, and that the throughput increases almost linearly with the number of PEs. Comparing with a software implementation running in a PC, the cGA with 64 PEs has shown a 45x speedup.

Because Richards' equation for describing unsaturated groundwater flow is highly nonlinear, it is challenging to test the accuracy and efficiency of parallel three-dimensional finite element groundwater programs used to model such activities as remediation of military sites and computing flows and pressures in levees broken by Hurricane Katrina. To aid in this testing, the author has derived steady-state and transient analytical solutions for unsaturated flow. With these solutions, both accuracy of the numerical solutions and the performance of the parallel versions of the computer programs may be easily tested. The other significant feature of these analytical solutions is that the amount of nonlinearity of the equation may be easily adjusted by a parameter a. This paper first presents the equations for the analytical solutions of steady-state and transient flow into a rectangular block of initially dry soil. It then uses the program FEMWATER as a benchmark to compute the numerical solutions corresponding to these analytical solutions. Accuracy results for various sizes of the mesh and numbers of processing elements (PEs) on the Cray XT3 are computed for different values of a. The number of nonlinear iterations for the steady-state problem is also reported. The result of the accuracy assessment is that as a is increased, the errors also increase significantly with even 512 PEs not being enough compute power to adequately solve the problem. Overall parallel performance and performance of the message passing interface calls for updating the ghost nodes and are also tested with results given. The result of this study is that scaling of a 1,000,000-element problem was good up to 256 PEs (64 PEs is the typical sweet spot for FEMWATER), and the performance of the ghost-node updating routine met or exceeded expectations

Multimedia applications are among the most dominant computing workloads driving innovations in high performance and cost effective systems. In this regard, modern general-purpose microprocessors have included multimedia extensions (e.g., MMX, SSE, VIS, MAX, ALTIVEC) to their instruction set architectures to improve the performance of multimedia with little added cost to microprocessors. Whereas prior studies of multimedia extensions have primarily focused on a single processor, this paper quantitatively evaluates the impact of multimedia extensions on system performance and efficiency for different number of processing elements (PEs) within an integrated multiprocessor array. This paper also identifies the optimal PE granularity for the array system and implementation technology in terms of throughput, area efficiency, and energy efficiency using architectural and workload simulation. Experimental results with cycle accurate simulation and technology modeling show that MMX-type instructions (a representative Intel’s multimedia extensions) achieve an average speedup ranging from 1.24( (at a 65,536 PE system) to 5.65( (at a 4 PE system) over the baseline performance. In addition, the MMX-enhanced processor array increases both area and energy efficiency over the baseline for all the configurations and programs. Moreover, the highest area and energy efficiency are achieved at the number of PEs between 256 and 1,024. These evaluation techniques composed of performance simulation and technology modeling can provide solutions to the design challenges in a new class of multiprocessor array systems for multimedia.

Fine grain VLSI array processors for real-time 2-D state-space digital filters are designed and evaluated. The architecture of the VLSI array processors is a linear systolic array, of which processing elements (PEs) are simple and homogeneous 1-D state-space digital filters. The number of PEs is equal to the number of rows of the processing images. A hierarchical behavioral description language and a synthesizer are utilized for the design and evaluation of the VLSI array processors. One VLSI chip is composed of 129 k gates and is integrated into one 14.70 /spl times/ 14.98 mm/sup 2/ VLSI chip using 1-/spl mu/m CMOS technology. Eight PEs can be integrated into one VLSI chip. The fine grain VLSI chips at 25 MHz clock can process a 1,024 /spl times/ 1,024 image in 1.47 msec, and can be applied to real-time video signal processing. >

Horizon is a shared-memory multiple-instruction-stream-multiple-data-stream architecture currently under study. The performance of one Horizon processing element (PE) is quantified by user operations per instruction, the instructions per tick, and the basic clock rate. Assuming there is sufficient parallelism within a problem, the performance of one PE is multiplied by the number of PEs contained in the Horizon system. For a 256-PE Horizon the expected sustained performance is on the order of 50 billion user operations per second for problems with sustained parallelism of 8000 to 12000 instruction streams.

Upcoming processor architectures support parallel processing on different levels. Multiple processing elements (PEs) run in parallel. The PEs consists of several functional units and the functional units allow sub-word parallelism (SWP), i.e. the parallel execution of operations with low data word width. In this paper, a parameterized mapping of algorithms onto massively parallel processor architectures (PAs) is derived which exploits both parallelism on PA and SWP on PE level. It establishes a correlation between the parameters of the algorithms and the parameters of the PA, which enables optimization strategies with respect to several expense factors of the PA. The design approach is based on the co-partitioning method and the partitioning of data dependencies. Both are used in a hierarchical manner. Besides the parameters of the PA (such as shape, number of PEs, number of sub-words processed in parallel, channels between the PEs, and their delay), the packing instructions for exploiting SWP can be deduced

Pairwise sequence alignment forms the basis of numerous other applications in bioinformatics. The quality of an alignment is gauged by statistical significance rather than by alignment score alone. Therefore, accurate estimation of statistical significance of a pairwise alignment is an important problem in sequence comparison. Recently, it was shown that pairwise statistical significance does better in practice than database statistical significance, and also provides quicker individual pairwise estimates of statistical significance without having to perform time-consuming database search. Under an evolutionary model, a substitution matrix can be derived using a rate matrix and a fixed distance. Although the commonly used substitution matrices like BLOSUM62, etc. were not originally derived from a rate matrix under an evolutionary model, the corresponding rate matrices can be back calculated. Many researchers have derived different rate matrices using different methods and data. In this paper, we show that pairwise statistical significance using rate matrices with sequence-pair-specific distance performs significantly better compared to using a fixed distance. Pairwise statistical significance using sequence-pair-specific distanced substitution matrices also outperforms database statistical significance reported by BLAST.

Tan spot of wheat, caused by Pyrenophora tritici-repentis, provided a model system for testing disease forecasts based on an artificial neural network. Infection periods for P. tritici-repentis on susceptible wheat cultivars were identified from a bioassay system that correlated tan spot incidence with crop growth stage and 24-h summaries of environmental data, including temperature, relative humidity, wind speed, wind direction, solar radiation, precipitation, and flat-plate resistance-type wetness sensors. The resulting data set consisted of 97 discrete periods, of which 32 were reserved for validation analysis. Neural networks with zero to nine processing elements were evaluated 20 times each to identify the model that most accurately predicted an infection event. The 200 models averaged 74 to 77% accuracy, depending on the number of processing elements and random initialization of coefficients. The most accurate model had five processing elements and correctly predicted 87% of the infection periods in the validation set. In comparison, stepwise logistic regression correctly predicted 69% of the validation cases, and multivariate discriminant analysis distinguished 50% of the validation cases. When wetness-sensor inputs were withheld from the models, both the neural network and logistic regression models declined 6% in prediction accuracy. Thus, neural networks were more accurate than statistical procedures, both with and without wetness-sensor inputs. These results demonstrate the applicability of neural networks to plant disease forecasting.

Pattern matching or finding the occurrences of a pattern in a text arises frequently in many applications. The task of splitting the character stream or text into words is called tokenization. Search engines use tokenizers. The first phase of a compiler outputs a stream of tokens of the given high-level language program. The pattern rules are specified as regular expressions. Many tools have been developed in the past that generate the tokenizer automatically which are mostly sequential. The advent of multicore architectures has made it mandatory to use its features like multiple threads and SIMD instructions in generating software tools. This works attempts to parallelize tokenization. This is a simple prototype implementation of a parallelized lexical analyzer that recognizes the tokens of the given source code. Each Synergetic Processing Element (SPE) of the cell processor works on a block of source code and tokenizes them independently. The Power Processing Unit (PPE) is responsible for splitting the source code into a finite number of blocks to be used by the different processing elements. Each SPE sends the stream of identifiers to the PPE which maintains the symbol table. The parallel lexical analyzer developed runs on IBM Cell Processor simulator and the execution times are plotted varying the code size and the number of processing elements.

The authors address a parallel algorithm for handwriting feature extraction on a RPM (reconfigurable parallel machine). Introducing the novel parallel architecture RPM, the authors have developed a very effective algorithm for feature extraction. The feature of handwriting is represented as a graph called a pattern graph. The proposed parallel feature extraction algorithm executes in O(1) time, while conventional algorithms require O(N/sup 2/) time, where N /spl times/ N is the size of input image. Dramatic improvement in execution time is due to the pixel per PE (processing element) mapping and the distributed programmable interconnection network. The number of PEs can be reduced by multiplexing a group of virtual PEs onto one PE.

Convolutional Neural Networks (CNNs) have been shown to be very useful in image recognition and other AI applications. CNNs are usually computationally intensive. To address the challenge of overwhelming calculation requirements, researchers have proposed network compression methods to reduce the number of synaptic weights and the amount of computations. In this paper, we propose an input row based sparse convolution neural network accelerator on FPGAs that performs sparse CNN computing efficiently. Similar to the DNNWEAVER architecture, our accelerator also uses two-level architecture hierarchy, with multiple Processing Units (PUs) and each PU comprises a set of basic Processing Elements (PEs). The number of PEs in a single PU and the number of PUs in a design are reconfigurable for different CNNs for best performance. Our architecture does not require the large multiplexer for data selection as needed in Cambricon-X, thus, is more suitable for larger accelerator designs for high performance. Besides, we propose a weight merging method to balance the computation load on different PUs to maximize the overall computation efficiency. For evaluation, we implement our design with 32 PUs and each with 14 PEs. When compared with the DNNWEAVER implementation for non-sparse VGG16 network, we get an overall performance of 3.6x speedup running at 100MHz on a Xilinx ZC706 board and reach the speed of 297 GOPS.