Parallel Lexical Analyzer on the Cell Processor

The authors address a parallel algorithm for handwriting feature extraction on a RPM (reconfigurable parallel machine). Introducing the novel parallel architecture RPM, the authors have developed a very effective algorithm for feature extraction. The feature of handwriting is represented as a graph called a pattern graph. The proposed parallel feature extraction algorithm executes in O(1) time, while conventional algorithms require O(N/sup 2/) time, where N /spl times/ N is the size of input image. Dramatic improvement in execution time is due to the pixel per PE (processing element) mapping and the distributed programmable interconnection network. The number of PEs can be reduced by multiplexing a group of virtual PEs onto one PE.

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The "divide and conquer" technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(?V?1/2) for the processor arrays considered in this paper, where ?V? is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.

Massively parallel computers have been used for high performance computation in advanced science and technology. The Hypercube (HC) network: has attractive properties such as strong connectivity, recursive interconnection, simple routing, and a good link complexity. However, as the number of processing elements (PEs) increases, the diameter and average distance of HC become large in proportion to a logarithm of the number of PEs. This causes a large latency in communication between PEs and consequently, it reduces system performance. To solve this problem, two approaches have been investigated. The first approach is a theoretical approach to find a network topology reducing a diameter and an average distance between PEs. The second approach reduces the physical distances between PEs by integrating a large interconnection on a small chip for a silicon wafer. In this paper, we propose a new interconnection network; The HCQ (Horizontal Rotate Crossed Cube) by taking into account a WSI implementation, Theoretical network properties such as the diameter, the average distance, a routing algorithm are discussed in detail. It is shown that HCQ is a suitable network topology for massively parallel computers for WSI.

Cellular Genetic Algorithms (cGAs) exhibit a natural parallelism that makes them interesting candidates for hardware implementation, as several processing elements can operate simultaneously on subpopulations shared among them. This paper presents a scalable architecture for a cGA, suitable for FPGA implementation. A regular array of custom designed processing elements (PEs) works on a population of solutions that is spread into dual-port memory blocks locally shared by adjacent PEs. A travelling salesman problem with 150 cities was used to verify the implementation of the proposed cGA on a Virtex-6 FPGA, using a population of 128 solutions with different levels of parallelism (1, 4, 16 and 64 PEs). Results have shown that an increase of the number of PEs does not degrade the quality of the convergence of the iterative process, and that the throughput increases almost linearly with the number of PEs. Comparing with a software implementation running in a PC, the cGA with 64 PEs has shown a 45x speedup.

This paper presents a novel substitution matrix loader architecture for pairwise sequence alignment. The search for sequence homology using DP-based alignment matrix computation is an important tool in molecular biology. It can be implemented either by optimal or sub-optimal approaches. Both of these methods require frequent and rapid access to the amino acids probability scores for PE (Processing Element) configuration especially in a folded systolic array. Typical FPGA implementations configure look-up tables in the pipeline PEs either by using a serial configuration chain with different look-up tables or by run time reconfiguration of the same look-up table. In the former case, configuration time increases proportionally to the number of look-up tables, while the latter case suffers from the limited reconfiguration bandwidth. Therefore, in this paper, we propose a highly efficient parallel loader to optimize both time and space complexities of protein sequence alignment in folded systolic arrays, using only two configuration elements (CEs). In addition, the proposed loader enables PEs to be updated with substitution matrix scores concurrently, with the worst case configuration time of 2 × the depth of the PE's look-up table (in clock cycles). This allows for further optimization of the most time consuming alignment matrix computation through efficient scheduling of alignment matrix computation and PE configuration. Implementation results show that the proposed architecture achieves k.N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PE</sub> speed-up in configuration time (where k is the folding factor and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PE</sub> is the number of PEs) compared to classical approaches, at virtually no area overhead.

The CELL architecture has one Power Processor Element (PPE) core, and eight Synergistic Processor Element (SPE) cores that have a distinct instruction set architecture of their own. The PPE core accesses memory via a traditional caching mechanism, but each SPE core can only access memory via a small 256K software-controlled local store. The PPE cache and SPE local stores are connected to each other and main memory via a high bandwidth bus. Software is responsible for all data transfers to and from the SPE local stores. To hide the high latency of DMA transfers, data may be prefetched into SPE local stores using loop blocking transformations and static buffers. We find that the performance of an application can vary depending on the size of the buffers used, and whether a single-, double-, or triple-buffer scheme is used. Constrained by the limited space available for data buffers in the SPE local store, we want to choose the optimal buffering scheme for a given space budget. Also, we want to be able to determine the optimal buffer size for a given scheme, such that using a larger buffer size results in negligible performance improvement. We develop a model to automatically infer these parameters for static buffering, taking into account the DMA latency and transfer rates, and the amount of computation in the application loop being targeted. We test the accuracy of our prediction model using a research prototype compiler developed on top of the IBM XL compiler infrastructure.

Because Richards' equation for describing unsaturated groundwater flow is highly nonlinear, it is challenging to test the accuracy and efficiency of parallel three-dimensional finite element groundwater programs used to model such activities as remediation of military sites and computing flows and pressures in levees broken by Hurricane Katrina. To aid in this testing, the author has derived steady-state and transient analytical solutions for unsaturated flow. With these solutions, both accuracy of the numerical solutions and the performance of the parallel versions of the computer programs may be easily tested. The other significant feature of these analytical solutions is that the amount of nonlinearity of the equation may be easily adjusted by a parameter a. This paper first presents the equations for the analytical solutions of steady-state and transient flow into a rectangular block of initially dry soil. It then uses the program FEMWATER as a benchmark to compute the numerical solutions corresponding to these analytical solutions. Accuracy results for various sizes of the mesh and numbers of processing elements (PEs) on the Cray XT3 are computed for different values of a. The number of nonlinear iterations for the steady-state problem is also reported. The result of the accuracy assessment is that as a is increased, the errors also increase significantly with even 512 PEs not being enough compute power to adequately solve the problem. Overall parallel performance and performance of the message passing interface calls for updating the ghost nodes and are also tested with results given. The result of this study is that scaling of a 1,000,000-element problem was good up to 256 PEs (64 PEs is the typical sweet spot for FEMWATER), and the performance of the ghost-node updating routine met or exceeded expectations

Multimedia applications are among the most dominant computing workloads driving innovations in high performance and cost effective systems. In this regard, modern general-purpose microprocessors have included multimedia extensions (e.g., MMX, SSE, VIS, MAX, ALTIVEC) to their instruction set architectures to improve the performance of multimedia with little added cost to microprocessors. Whereas prior studies of multimedia extensions have primarily focused on a single processor, this paper quantitatively evaluates the impact of multimedia extensions on system performance and efficiency for different number of processing elements (PEs) within an integrated multiprocessor array. This paper also identifies the optimal PE granularity for the array system and implementation technology in terms of throughput, area efficiency, and energy efficiency using architectural and workload simulation. Experimental results with cycle accurate simulation and technology modeling show that MMX-type instructions (a representative Intel’s multimedia extensions) achieve an average speedup ranging from 1.24( (at a 65,536 PE system) to 5.65( (at a 4 PE system) over the baseline performance. In addition, the MMX-enhanced processor array increases both area and energy efficiency over the baseline for all the configurations and programs. Moreover, the highest area and energy efficiency are achieved at the number of PEs between 256 and 1,024. These evaluation techniques composed of performance simulation and technology modeling can provide solutions to the design challenges in a new class of multiprocessor array systems for multimedia.

Fine grain VLSI array processors for real-time 2-D state-space digital filters are designed and evaluated. The architecture of the VLSI array processors is a linear systolic array, of which processing elements (PEs) are simple and homogeneous 1-D state-space digital filters. The number of PEs is equal to the number of rows of the processing images. A hierarchical behavioral description language and a synthesizer are utilized for the design and evaluation of the VLSI array processors. One VLSI chip is composed of 129 k gates and is integrated into one 14.70 /spl times/ 14.98 mm/sup 2/ VLSI chip using 1-/spl mu/m CMOS technology. Eight PEs can be integrated into one VLSI chip. The fine grain VLSI chips at 25 MHz clock can process a 1,024 /spl times/ 1,024 image in 1.47 msec, and can be applied to real-time video signal processing. >

Horizon is a shared-memory multiple-instruction-stream-multiple-data-stream architecture currently under study. The performance of one Horizon processing element (PE) is quantified by user operations per instruction, the instructions per tick, and the basic clock rate. Assuming there is sufficient parallelism within a problem, the performance of one PE is multiplied by the number of PEs contained in the Horizon system. For a 256-PE Horizon the expected sustained performance is on the order of 50 billion user operations per second for problems with sustained parallelism of 8000 to 12000 instruction streams.

Upcoming processor architectures support parallel processing on different levels. Multiple processing elements (PEs) run in parallel. The PEs consists of several functional units and the functional units allow sub-word parallelism (SWP), i.e. the parallel execution of operations with low data word width. In this paper, a parameterized mapping of algorithms onto massively parallel processor architectures (PAs) is derived which exploits both parallelism on PA and SWP on PE level. It establishes a correlation between the parameters of the algorithms and the parameters of the PA, which enables optimization strategies with respect to several expense factors of the PA. The design approach is based on the co-partitioning method and the partitioning of data dependencies. Both are used in a hierarchical manner. Besides the parameters of the PA (such as shape, number of PEs, number of sub-words processed in parallel, channels between the PEs, and their delay), the packing instructions for exploiting SWP can be deduced

Heterogeneous clusters that include accelerators have become more common in the realm of high performance computing because of the high GFlop/s rates such clusters are capable of achieving. However, heterogeneous clusters are typically considered hard to program as they usually require programmers to interleave architecture-specific code within application code. We have extended the Charm++ programming model and runtime system to support heterogeneous clusters (with host cores that differ in their architecture) that include accelerators. We are currently focusing on clusters that include commodity processors, Cell processors, and Larrabee devices. When our extensions are used to develop code, the resulting code is portable between various homogeneous and heterogeneous clusters that may or may not include accelerators. Using a simple example molecular dynamics (MD) code, we demonstrate our programming model extensions and runtime system modifications on a heterogeneous cluster comprised of Xeon and Cell processors. Even though there is no architecture-specific code in the example MD program, it is able to successfully make use of three core types, each with a different ISA (Xeon, PPE, SPE), three SIMD instruction extensions (SSE, AltiVec/VMX and the SPE's SIMD instructions), and two memory models (cache hierarchies and scratchpad memories) in a single execution. Our programming model extensions abstract away hardware complexities while our runtime system modifications automatically adjust application data to account for architectural differences between the various cores.

In this paper we report our experience in implementing and evaluating the Data-Driven Multithreading (DDM) model on a heterogeneous multi-core processor. DDM is a non-blocking multithreading model that decouples the synchronization from the computation portions of a program, allowing them to execute asynchronously in a dataflow manner. Thread dependencies are determined by the compiler/programmer while thread scheduling is done dynamically at runtime based on data availability. The target processor for this implementation is the Cell processor. We call this implementation the Data-Driven Multithreading Virtual Machine for the Cell processor (DDM- $$\hbox {VM}_c$$ ). Thread scheduling is handled in software by the Power Processing Element core of the Cell while the Synergistic Processing Element cores execute the program threads. DDM- $$\hbox {VM}_c$$ virtualizes the parallel resources of the Cell, handles the heterogeneity of the cores, manages the Cell memory hierarchy efficiently and supports distributed execution across a cluster of Cell nodes. DDM- $$\hbox {VM}_c$$ has been implemented on a single Cell processor with six computation cores, as well as, on a four Cell processor cluster with 24 computation cores. We present an in-depth performance analysis of DDM- $$\hbox {VM}_c$$ , using a suite of standard computational benchmarks. The evaluation shows that DDM- $$\hbox {VM}_c$$ scales well and tolerates scheduling overheads, memory and communication latencies effectively. Furthermore, DDM- $$\hbox {VM}_c$$ compares favorably with other platforms targeting the Cell processor, such as, the CellSs and Sequoia.

Tan spot of wheat, caused by Pyrenophora tritici-repentis, provided a model system for testing disease forecasts based on an artificial neural network. Infection periods for P. tritici-repentis on susceptible wheat cultivars were identified from a bioassay system that correlated tan spot incidence with crop growth stage and 24-h summaries of environmental data, including temperature, relative humidity, wind speed, wind direction, solar radiation, precipitation, and flat-plate resistance-type wetness sensors. The resulting data set consisted of 97 discrete periods, of which 32 were reserved for validation analysis. Neural networks with zero to nine processing elements were evaluated 20 times each to identify the model that most accurately predicted an infection event. The 200 models averaged 74 to 77% accuracy, depending on the number of processing elements and random initialization of coefficients. The most accurate model had five processing elements and correctly predicted 87% of the infection periods in the validation set. In comparison, stepwise logistic regression correctly predicted 69% of the validation cases, and multivariate discriminant analysis distinguished 50% of the validation cases. When wetness-sensor inputs were withheld from the models, both the neural network and logistic regression models declined 6% in prediction accuracy. Thus, neural networks were more accurate than statistical procedures, both with and without wetness-sensor inputs. These results demonstrate the applicability of neural networks to plant disease forecasting.

Convolutional Neural Networks (CNNs) have been shown to be very useful in image recognition and other AI applications. CNNs are usually computationally intensive. To address the challenge of overwhelming calculation requirements, researchers have proposed network compression methods to reduce the number of synaptic weights and the amount of computations. In this paper, we propose an input row based sparse convolution neural network accelerator on FPGAs that performs sparse CNN computing efficiently. Similar to the DNNWEAVER architecture, our accelerator also uses two-level architecture hierarchy, with multiple Processing Units (PUs) and each PU comprises a set of basic Processing Elements (PEs). The number of PEs in a single PU and the number of PUs in a design are reconfigurable for different CNNs for best performance. Our architecture does not require the large multiplexer for data selection as needed in Cambricon-X, thus, is more suitable for larger accelerator designs for high performance. Besides, we propose a weight merging method to balance the computation load on different PUs to maximize the overall computation efficiency. For evaluation, we implement our design with 32 PUs and each with 14 PEs. When compared with the DNNWEAVER implementation for non-sparse VGG16 network, we get an overall performance of 3.6x speedup running at 100MHz on a Xilinx ZC706 board and reach the speed of 297 GOPS.