A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme

This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2n −1, 2n, 2n+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28% faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.

This paper focuses on SIMD implementations of the 2D discrete wavelet transform (DWT). The transforms considered are Daubechies' real-to-real method of four coefficients (Daub-4) and the integer-to-integer (5, 3) lifting scheme. Daub-4 is implemented using SSE and the lifting scheme using MMX, and their performance is compared to C implementations on a Pentium 4 processor. The MMX implementation of the lifting scheme is up to 4.0/spl times/ faster than the corresponding C program for a 1-level 2D DWT, while the SSE implementation of Daub-4 is up to 2.6/spl times/ faster than the C version. It is shown that for some image sizes, the performance is significantly hampered by the so called 64K aliasing problem, which occurs in the Pentium 4 when two data blocks are accessed that are a multiple of 64K apart. It is also shown that for the (5, 3) lifting scheme, a 12-bit word size is sufficient for a 5-level decomposition of the 2D DWT for images of up to 10 bits per pixel.

In this paper, a memory efficient 2-D discrete wavelet transform (DWT) structure is presented for high-speed application. The architecture is based on the modified lifting scheme to reduce the critical path to one multiplier delay. In order to increase the speed of processing, four pipeline stages are introduced in the structure. The computation time for an N × N image is N2/4, as the throughput rate of the structure is four. The results after comparison reveal that the proposed architecture has a temporal memory lower than the other DWT architectures. The Z-scan method is employed to fetch the input data which suits the transpose unit design. Five registers and a multiplexer constitute a transpose unit, which is required to transpose the data between the row and the column processor. The proposed 2-D dual-scan DWT architecture has the merits of low latency, low control complexity and regular signal flow, making it suitable for a very large-scale integration (VLSI) implementation. The architecture is modelled in VHDL and synthesised with the CMOS 180 nm technology.

The discrete wavelet transform (DWT) has been shown to provide exceptionally efficient data compression for neural records. This paper describes area-power minimized hardware implementations of the lifting and B-spline DWT schemes for multi-level, multi-channel DWT and analyzes their performance tradeoffs for implantable neuroprosthetics. The lifting scheme is shown to be increasingly superior for a larger number of input channels.

In this report, we introduce a directionally adaptive three dimensional (3D) prediction to the non-separable 3D discrete wavelet transform (DWT). The proposed 3D DWT has less lifting steps and better prediction performance comparing to the existing separable 3D DWT with fixed filter coefficients. The 3D DWT can be applied to compress data volume of volumetric medical images or motion pictures. It is also applicable to analyze such kind of multi-dimensional signals. The proposed method has compatibility with the conventional DWT defined by the JPEG 2000 international standard.

Background: Discrete Wavelet Transform (DWT) is extensively useful in different Digital Signal Processing (DSP) applications. In this paper, Lifting scheme is introduced in three mother wavelets, which are Haar wavelet, Daubechies (db4) and Cohen-Daubechies-Feauveau (CDF) 9/7-tap wavelet also known as db9/7 wavelet. Method: In this work each of the architecture is compared with its Direct form. Haar wavelet is used to design the basic DWT architecture. Daubechies DWT (db4) orthogonal filters and Cohen-Daubechies-Feauveau (CDF) 9/7 bi-orthogonal wavelet filters are considered for DWT construction. Due to the uncomplicated design, lifting scheme provides less power consumption. Instead of set of filters, simple predict and update mechanism is introduced. The IEEE 754 floating point standard is used to represent the filter coefficients. The architectures are described in Verilog HDL and simulation is performed in Xilinx for FPGA implementation. All the architectures are synthesized in Cadence RC for 180 nm technology. Findings: The Lifting Scheme has 75-82% less power consumption and 27% area-efficiency than conventional DWT architectures. FPGA implementation is done using Altera Cyclone IV FPGA kit. Maximum operating frequency is 33.3MHz and 45MHz for 3-level and 1-level of decomposition respectively in DWT implementation. Conclusion: Due to the uncomplicated design, lifting scheme provides less power consumption. DWT designs are compared with respect to power consumption and area.

The paper gives us, a brief account of the design of 2D - discrete wavelet transform (DWT) implemented in VLSI architecture using Verilog HDL which achieves high speed computation. The main motive behind the development of the architecture is on giving efficient hardware utilization along with high operating speed and less number of clock cycles. To verify the proposed scheme, 2D DWT is applied on a grey image of size 128*128 to get all the four components (average, diagonal, horizontal and vertical), this wavelet decomposition is verified and obtained in Xilinx 14.2 version software using Verilog HDL; circuit is planned, modelled (simulated) in Verilog HDL, and finally the result is validated in FPGA Spartan 6 to get the output 2D-DWT computed image back. This is a single chip implementation where discrete wavelet transform can be used in VLSI design more efficiently than other transform. It is depicted that the operation carried out with specified processing speed of the designed architecture based on the proposed scheme is good than those of the other architectures designed using other existing schemes, and it has less hardware utilization.

This paper presents an efficient lattice structure based VLSI architecture of 2D discrete wavelet transform (DWT) for hierarchical image compression, which is scalable to extend to an arbitrary 2D DWT with M laps and J levels. The proposed architecture consists Of four 1D lattice filters, which processes in horizontal and vertical directions at the same time. The proposed lattice structure fits in a VLSI implementation due to its regularity and shows the period of N/sup 2//2 to compute an N/spl times/N image because the even and odd rows are processed simultaneously. Compared to conventional approaches, the proposed architecture shows shorter period to complete 2D DWT while requiring relatively less hardware resources. Therefore, the proposed architecture can be applied in real-time video signal processing such as JPEG-2000 and MPEG4, which require high speed processing. The process schedule using the data dependency graph, performance, and the required hardware cost are discussed.

There are several methods to implement DWT. But lifting scheme is preferred because it reduces the computational complexity and is easy to implement. 9/7 filter coefficient are used in lifting scheme since they are originally implemented in JPEG codec 2000. Much architecture were developed using lifting scheme. But the number of computations is more leading to less efficient architecture. As an existing work, CSD algorithm based parallel flipped lifting 2D DWT using dual-scan technique (CSDPF) is designed with the modified flipping scheme using Canonical Signed Digit(CSD) algorithm.In order to reduce the computations Flipping Structure for a Lifting based Discrete Wavelet Transform using Sub Expression Sharing (SES) is developed for image compression. To improve the computational efficiency, area and power requirements sub expression sharing technique is used. In the case where several multipliers are present in a network of operators, the savings is achieved by identifying common subexpressions and sharing the two most common subexpressions that is expected to save the number of additions. It reduces the arithmetic resources like shifter and adder in its implementation. Using SES method the number of computations is reduced to half of the total computations. Hence a computationally efficient architecture with area and power reduction by 32% and 5% respectively is designed. The various applications include fax transmission, satellite remote sensing, high definition television, storage and transmission of CT and MRI scans etc.

The 3D Discrete Wavelet Transform (DWT) and Support Vector Machine (SVM) are used in this study to analyze and characterize Electrocardiogram (ECG) signals. This technique consists of three stages: ECG signal preprocessing, feature extraction, and ECG signal order. The 3D wavelet transform is a signal preprocessing technique, de-noising, along with wavelet coefficient extraction.•SVM is used to categorize the ECG through each of the nine heartbeat types recognized by the various classifiers. For this work, around 6400 ECG beats were looked at over the China Physiological Signal Challenge (CPSC) 2018 arrhythmia dataset.•The best degree of exactness was acquired when level 4 rough constants with Symlet-8 (Sym8) channel were utilized for arrangement. Utilizing the ECG signals from CPSC 2018 data set, the SVM classifier has a normal precision of 99.02%, which is much better than complex support vector machine (CSVM) 98.5%, and weighted support vector machine (WSVM) 99%.•The suggested approach is far superior to others in terms of accuracy, and classification of several diseases of arrhythmia.

A fine-grain load-adaptive algorithm of the 2D discrete wavelet transform for multithreaded architectures

For an effective communication system whether indoor or outdoor, the most important concern is minimum noise. In this paper, an efficient noise reduction technique is presented using various wavelet transform techniques for indoor optical wireless communication system (IOWC). In IOWC system, Fluorescent Light Interference (FLI) is main source of noise. Here, in this paper three methods are used to reduce the effect of noise from a digital signal. These are Discrete Wavelet Transform (DWT), Stationary Wavelet transform (SWT) and Discrete Wavelet transform-Stationary Wavelet Transform (DWT-SWT). Through sub band coding in DWT the signal is decomposed into lower sub bands of high and low frequency respectively of unequal size; while in SWT the decomposed signal have sub bands of equal size. In DWT-SWT the high frequency components of both DWT and SWT are added. Using Pulse Position Modulation, the comparison between these three techniques is described here to enhance the overall performance of the IOWC system.

This paper presents efficient single-rate architectures for the orthonormal discrete wavelet transform (DWT). Folded and digit-serial architectures are derived from an efficient lattice implementation of two-channel FIR paraunitary systems known as the quadrature mirror filter (QMF) lattice. Folded architectures are derived by applying systematic folding techniques to multirate systems. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The number of multipliers and adders required for both the folded and digit-serial lattice-based architectures approaches one-half the number required to implement similar systems based on direct-form filter implementations as the order of the FIR filters becomes large. This makes folded and digit-serial QMF lattice structures attractive choices for applications of the orthonormal DWT which require low area and low power dissipation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we propose two scalable architecture's (called Arc/sub J/ and Arc*/sub 2/) which perform the Discrete Wavelet Transform (DWT) of an N/sub 0/-sample sequence in only N/sub 0//2 clock cycles. Therefore, they are at least twice as fast as the known architectures. Also, their AT/sup 2/ parameter is approximately 1/2 of that of already existing devices. These results allow either a twice faster processing than that allowed by other architectures working at the same clock frequency (High-Speed utilization), or using a twice lower clock frequency, while reaching the same performance as other architectures. This second possibility permits reducing the power dissipation by a factor of 4 with respect to other architectures (Low-Power utilization). Finally, we shall show that an impressively efficient architecture can be defined as the synthesis of Arc/sub J/ and Arc*/sub 2/ (average efficiency=99.1%, minimum efficiency=93.8%).

The Discrete Wavelet Transform (DWT) is a signal processing technique popularised by its results in data compression. Considerable work has been done in designing novel architectures to perform the DWT, including a systolic architecture designed by the authors, but little attention has been given to the inverse DWT which is needed in applications such as data compression for signal reconstruction. Despite the fact that the inverse DWT is computationally the reverse of the DWT, the hardware design for the architecture is not simply mirrored. Existing designs expect the architecture for the inverse DWT to be a simple follow-on step from the DWT design, however this is not the case. We present one such problem here, showing the FIFO buffering required on the input of the inverse architecture. We show how the size of this buffer can be calculated and compare it to a fixed data array implementation. This work is based on our systolic array design and is an integral part of the inverse DWT design we are working on for image and video compression.