2D Lifting Based Discrete Wavelet Transform Architecture based on Sub Expression Reduction Technique

Hamming weight pyramid – A new insight into canonical signed digit representation and its applications

This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley's technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. An algorithm is given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using MILP. Utilization of common expressions in Hartley's technique widen the CSD coefficient space. Thus the mixed integer linear programming (MILP) may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations.

We present a technique for the design of multiplierless FIR filters with canonic signed digit (CSD) coefficients based on higher order sigma-delta modulation with a CSD quantizer (/spl Sigma//spl Delta/-CSD). The CSD quantizer yields FIR filter coefficients quantized to sums of a few signed powers-of-two digits, eliminating the need for multiplication. The sigma-delta modulation moves the quantization error out of the band of interest into a frequency band where the increased error can be attenuated by a cascaded prefilter in a prefilter-equalizer structure, or be attenuated by a decimation filter in a multi-rate approach. The use of higher order sigma-delta modulation provides more flexibility in moving the quantization error than the previously proposed first-order modulation. We give lowpass and bandpass examples where the filters designed by the higher order modulation demonstrate substantial frequency characteristic improvement. An empirical design guideline to ensure the stability for the higher order /spl Sigma//spl Delta/-CSD modulation is also given in the paper.

Common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the coefficient multipliers in digital filters. Two classes of common subexpressions (CS) occur in the canonic signed digit (CSD) representation of coefficients, called the horizontal and the vertical CS. Previous works have not addressed the trade-offs in using these two types of CS on the delay and the number of multiplier block adders. We provide a comparison of hardware reductions achieved using the horizontal and the vertical CS in realizing digital filters. We show that the CSE technique employing horizontal CS offers better reductions in the number of adders and critical paths than its vertical CS counterpart in practical linear phase finite impulse response (LPFIR) filter implementations. Our simulation results show that the hardware reductions offered by the vertical CS in implementing infinite impulse response (IIR) filters are improved compared to their LPFIR counterparts.

In this paper, we propose a highly efficient VLSI architecture for 2-D dual-mode (supporting 5/3 and 9/7 lifting-based) Symmetric Mask-based Discrete Wavelet Transform (SMDWT) to improve the critical issue of the 2-D Lifting-based Discrete Wavelet Transform (LDWT), and then obtains the benefit of low-latency reduced complexity, and low transpose memory. The SMDWT also has the advantages of reduced complexity, regular signal coding, short critical path, reduced latency time, and independent subband coding processing. The transpose memory requirement of the N×N is 9N. The architecture is based on the parallel and folding scheme processing to achieve higher hardware utilization ratio and reduce the silicon area. It is suitable for Very Large Scale Integration (VLSI) implementation and can be applied to real-time operating of computer vision applications.

With the development of science and technology, Sigma-Delta (∑-A) ADCs are widely used in various fields of electronics with their flexible advantages. As an essential component of a Sigma-Delta ADC, digital filters directly and significantly impact the ADC's accuracy, delay, and power consumption. This paper presents a multistage digital filter for 18-bit ∑-A ADCs; the filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC's accuracy. The filter's order and downsampling multiplier are designed using canonical signed digit (CSD) and common subexpression (CSE) to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 0.18 µm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, total power of 518.35 uW, and a Digital filter power of 82.93 uW, which effectively reduces the power consumption while improving the accuracy.

Low complexity reconfigurable channelizers using non-uniform filter banks

Adjustable window based design of multiplier-less cosine modulated filter bank using swarm optimization algorithms

In this paper, a high-efficient lined-based architecture for the 9/7 discrete wavelet transform (DWT) based on lifting scheme is proposed. The proposed parallel and pipelined architecture consists of a horizontal filter (HF) and a vertical filter (VF). The critical path of the proposed architecture is reduced. Filter coefficients of the biorthogonal 9/7 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architecture, all multiplications are performed using less shifts and additions. The proposed architecture is 100% hardware utilization and ultra low-power. The architecture has regular structure, simple control flow, high throughput and high scalability. Thus, it is very suitable for new-generation image compression systems, such as JPEG-2000.

A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

이 논문에서는 OFDM Modem의 심볼 타이밍 옵셋 동기화 블록에 대한 저면적 구조를 제안한다. 심볼 타이밍 동기화 블록에서의 곱셈연산을 디지털 필터 구조의 개념을 도입하여 저면적 구조를 유도하였다. 즉 곱셈연산을 CSD(Canonic Signed Digit) 방식과 CSS(Common Sub-expression Sharing) 방식의 덧셈기를 사용한 구조를 제안하였다. 제안 구조에 대한 Verilog-HDL 코딩과 합성을 통하여 <TEX>$0.264mm^2$</TEX>로 구현하였으며, 이는 기존 구조의 <TEX>$0.723mm^2$</TEX>와 비교하여 63.54%의 구현 면적 감소를 달성하였다. 따라서 제안된 구조는 OFDM 시스템의 심볼 타이밍 동기화기에 효율적으로 사용 될 수 있을 것이다. In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

In this paper, we present a memory efficient VLSI architecture for 2-D Discrete Wavelet Transform (DWT) using lifting scheme. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. It decomposes the wavelet transform with finite taps into two coefficient sets named predictor and updater. Base on the lifting scheme, we explore its data dependency of input and output signals, and thus propose a programmable architecture for different filter banks with low memory usage. For the computation of N/spl times/N 2-D DWT with Daubechies 9-7 filter, our architecture requires 9N storage cells and the memory bandwidth requirement is almost one-half of JPEG2000's proposal. This architecture is suitable for VLSI implementation and various real-time image/video applications.

This paper presents a method to find the minimum number of adders for implementing a multiplier of a given multiplicand and the corresponding structure to realize it. In comparison with the widely used structure based on the canonic signed digit (CSD) expression of multiplicands, the number of adders required by using our structure is not more than that of the CSD structure for any multiplicand. The contiguous range of integer multiplicands whose corresponding multiplications can be implemented by no more than a given number of adders increases exponentially with the increase of the number of adders allowed. It is shown that the ratio of the largest contiguous integer range of our structure to that of the CSD structure is equal to 10.76 and 64.43, respectively, for using no more than 4 and 5 adders. Our method for replacing multipliers with shifters and adders is applied to the design of multiplierless digital filters. Experimental results show that the normalized peak ripples of the filters designed by our method is decreased by up to 4.2 dB over those obtained by the corresponding design method based on the CSD expression of filter coefficients.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This work presents a proficient approach of designing an M-band Near Perfect Reconstruction (NPR) Cosine Modulated Filter Bank (CMFB) where the NPR condition is built upon to satisfy the power complementary property and the pass-edge frequency is repetitively varied to adjust the filter-coefficients to reduce the reconstruction error occurred. Using this optimal value of the pass-edge frequency, the prototype filter is designed and the filter bank is considered from that single prototype filter. Thus the primary goal of designing the CMFB comes down to the issue of implementing efficient structure of this prototype filter. Now the prototype filter is designed with Interpolated Finite Impulse Response (IFIR) technique where numbers of hardware multipliers are reduced by cascading model and image suppression filter compared to that of single prototype filter and furthermore the designed filter coefficients are replaced with Canonical Signed Digit (CSD) to get lesser hardware complexity. To make the system practically realizable, an Electrocardiogram (ECG) signal is processed through this system and reconstructed back again. Some quality measurement parameters such as Signal-to-Noise Ratio (SNR), Mean Square Error (MSE) and Percentage Root Mean Square Difference (PRD) are analyzed to see the effectiveness of the CMFB.

A problem was identified as being caused by the Canonical Signed Digit (CSD) generated during the calculation and selection of filter coefficients for higher-order FIR filters, as revealed by the study that was provided. It is also discussed how to use a second approach, known as canonical signed digits-based coefficients computation, which provides a distinct advantage in the overall process of developing, selecting, and executing FIR filters, while also being more energy efficient in terms of power consumption. A software tool called CSDFIR, which implements the recommended design technique, can be used to generate Chebyshev optimum floating point and fixed point CSD FIR filters.