A Study on Chebyshev Filter Design by Using CSD

We present a technique for the design of multiplierless FIR filters with canonic signed digit (CSD) coefficients based on higher order sigma-delta modulation with a CSD quantizer (/spl Sigma//spl Delta/-CSD). The CSD quantizer yields FIR filter coefficients quantized to sums of a few signed powers-of-two digits, eliminating the need for multiplication. The sigma-delta modulation moves the quantization error out of the band of interest into a frequency band where the increased error can be attenuated by a cascaded prefilter in a prefilter-equalizer structure, or be attenuated by a decimation filter in a multi-rate approach. The use of higher order sigma-delta modulation provides more flexibility in moving the quantization error than the previously proposed first-order modulation. We give lowpass and bandpass examples where the filters designed by the higher order modulation demonstrate substantial frequency characteristic improvement. An empirical design guideline to ensure the stability for the higher order /spl Sigma//spl Delta/-CSD modulation is also given in the paper.

This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley's technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. An algorithm is given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using MILP. Utilization of common expressions in Hartley's technique widen the CSD coefficient space. Thus the mixed integer linear programming (MILP) may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations.

In a preceding paper, it was shown that the canonical signed-digit (CSD) representation of the multiplier coefficients in frequency response-masking (FRM) FIR digital filters leads to a substantial reduction in the hardware complexity of the FIR digital filter. However, a direct approximation of the infinite-precision multiplier coefficients to their CSD counterparts may cause the FIR digital filter to cease to satisfy the given filter design specifications. This paper presents a novel technique based on diversity controlled (DC) genetic algorithm (GA) for the discrete optimization of FRM FIR digital filters over the CSD multiplier coefficient space. The salient feature of the DCGA technique is that it permits external control over population diversity and parent selection pressure, giving rise to a rapid convergence to an optimal solution. It is shown that the application of the proposed DCGA technique to the optimization of a benchmark low-pass FRM digital filter over CSD multiplier coefficient space leads to an order of magnitude speed-up factor as compared to that associated with a conventional GA. Moreover, the optimized CSD FRM digital filter outperforms the corresponding infinite-precision digital filter obtained by the classical Parks-Mclellan approach.

Hamming weight pyramid – A new insight into canonical signed digit representation and its applications

This work combines two distinct research efforts, the coefficient design and the adder-number reduction, of fixed-point FIR filters into an automatic design flow. Given the normalized peak-ripple-magnitude (NPRM) specifications, the canonic-signed-digit (CSD) filter coefficients are calculated by the partial mixed-integer-linear-programming (PMILP) algorithm. Then a signed common subexpression sharing (SCSS) algorithm is used to reduce the number of adders required to implement the FIR filter. Finally a VHDL code that describes the FIR filter hardware with SCSS is generated.

This paper presents a method to find the minimum number of adders for implementing a multiplier of a given multiplicand and the corresponding structure to realize it. In comparison with the widely used structure based on the canonic signed digit (CSD) expression of multiplicands, the number of adders required by using our structure is not more than that of the CSD structure for any multiplicand. The contiguous range of integer multiplicands whose corresponding multiplications can be implemented by no more than a given number of adders increases exponentially with the increase of the number of adders allowed. It is shown that the ratio of the largest contiguous integer range of our structure to that of the CSD structure is equal to 10.76 and 64.43, respectively, for using no more than 4 and 5 adders. Our method for replacing multipliers with shifters and adders is applied to the design of multiplierless digital filters. Experimental results show that the normalized peak ripples of the filters designed by our method is decreased by up to 4.2 dB over those obtained by the corresponding design method based on the CSD expression of filter coefficients.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

There are several methods to implement DWT. But lifting scheme is preferred because it reduces the computational complexity and is easy to implement. 9/7 filter coefficient are used in lifting scheme since they are originally implemented in JPEG codec 2000. Much architecture were developed using lifting scheme. But the number of computations is more leading to less efficient architecture. As an existing work, CSD algorithm based parallel flipped lifting 2D DWT using dual-scan technique (CSDPF) is designed with the modified flipping scheme using Canonical Signed Digit(CSD) algorithm.In order to reduce the computations Flipping Structure for a Lifting based Discrete Wavelet Transform using Sub Expression Sharing (SES) is developed for image compression. To improve the computational efficiency, area and power requirements sub expression sharing technique is used. In the case where several multipliers are present in a network of operators, the savings is achieved by identifying common subexpressions and sharing the two most common subexpressions that is expected to save the number of additions. It reduces the arithmetic resources like shifter and adder in its implementation. Using SES method the number of computations is reduced to half of the total computations. Hence a computationally efficient architecture with area and power reduction by 32% and 5% respectively is designed. The various applications include fax transmission, satellite remote sensing, high definition television, storage and transmission of CT and MRI scans etc.

A programmable FIR digital filter based on canonical-signed-digit (CSD) computation sharing multiplier is presented in this paper. The proposed CSD-based computation sharing multiplier can not only relax the critical path but also reduce the hardware cost compared to the binary computation sharing multiplier. It can reduce the cost by 44% of the binary computation sharing FIR filter with 112% clock speed. Moreover, the cost and speed of the programmable FIR digital filter are also simulated and analyzed in terms of the precomputation alphabet bitwidth, the multiplier resolution, and the number of filter tap. The results show that the optimal cost and speed can be more easily obtained at the same time in the CSD-based computation sharing programmable FIR filter than in the binary approach.

This article discusses the design of FIR filters that approximate a complex-valued target frequency response in a Chebyshev sense. Additionally, the required stopband attenuation can be specified. Solving the dual of a semi-infinite linear program is currently the most efficient way to design such filters, but numerical problems prevent the design of high-order FIR filters. Modifications are proposed to overcome this limitation. Furthermore, an efficient method is presented for generating starting values that are close to the optimal solution such that the number of iterations is considerably reduced. Examples of filters with a length up to 250 taps are included.

This work presents a proficient approach of designing an M-band Near Perfect Reconstruction (NPR) Cosine Modulated Filter Bank (CMFB) where the NPR condition is built upon to satisfy the power complementary property and the pass-edge frequency is repetitively varied to adjust the filter-coefficients to reduce the reconstruction error occurred. Using this optimal value of the pass-edge frequency, the prototype filter is designed and the filter bank is considered from that single prototype filter. Thus the primary goal of designing the CMFB comes down to the issue of implementing efficient structure of this prototype filter. Now the prototype filter is designed with Interpolated Finite Impulse Response (IFIR) technique where numbers of hardware multipliers are reduced by cascading model and image suppression filter compared to that of single prototype filter and furthermore the designed filter coefficients are replaced with Canonical Signed Digit (CSD) to get lesser hardware complexity. To make the system practically realizable, an Electrocardiogram (ECG) signal is processed through this system and reconstructed back again. Some quality measurement parameters such as Signal-to-Noise Ratio (SNR), Mean Square Error (MSE) and Percentage Root Mean Square Difference (PRD) are analyzed to see the effectiveness of the CMFB.

In this paper, a design method of CSD (Canonic Signed Digit) coefficient FIR (Finite Impulse Response) filters using GA (Genetic Algorithm) is described. In GA, individuals tend to have similar genetic structure as the number of iterations increases. Therefore, a new strategy using multiple populations under different constraints was proposed to keep a successive diversification. However, a detail effectiveness of strategy is not verified. In this paper, several design examples are shown to present the effectiveness of multiple population GA for the CSD coefficient FIR filter design.

A novel design and implementation technique for low complexity variable digital filters using multi-objective artificial bee colony optimization and a minimal spanning tree approach

With the development of science and technology, Sigma-Delta (∑-A) ADCs are widely used in various fields of electronics with their flexible advantages. As an essential component of a Sigma-Delta ADC, digital filters directly and significantly impact the ADC's accuracy, delay, and power consumption. This paper presents a multistage digital filter for 18-bit ∑-A ADCs; the filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC's accuracy. The filter's order and downsampling multiplier are designed using canonical signed digit (CSD) and common subexpression (CSE) to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 0.18 µm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, total power of 518.35 uW, and a Digital filter power of 82.93 uW, which effectively reduces the power consumption while improving the accuracy.

A pipelinable bit-serial multiplier using Canonic Signed Digit, or CSD code to represent constant coefficients is introduced. A bit-serial module for a(x/spl plusmn/y)z/sup -1/ type computation is further developed. Optimization over discrete power-of-two coefficient space has been retargeted on this type of multiplier to generate minimized no-zero bit coefficients. This also make it possible to confine the latency to be equivalent to the data wordlength without causing a large delay in partial product sum propagation. A single chip FPGA implementation of a full 16-bit 31-tap Hilbert transformer is used as an example to demonstrate the application of the multiplier module with the special consideration of FPGA architectures. It is shown that FPGA architecture is an ideal vehicle for thus optimized bit-serial processing. >

Adjustable window based design of multiplier-less cosine modulated filter bank using swarm optimization algorithms