A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

Power efficient ultra-wideband based wireless communication for wireless body area network applications

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

This paper presents a high-speed, broadband phase -locked loop (PLL) for RF transceiver in 65nm CMOS process. Programmable structures are used to improve the lock speed of the PLL, the charge pump and loop filter can be adjusted by digital bit to reduce locked time of PLL. An integrated voltage-control oscillator (VCO) with 75% tuning range and a high-speed divider are used to accomplish all the frequencies. To achieve a wide tuning range while keep a low gain and a low phase noise, the VCO uses switched capacitor array. Finally, the PLL realizes 6-12 GHz wide frequency coverage. The phase noise performance at 6GHz is -113dBc/Hz@lMHz. The layout area is only 0.5265mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Working at 1. 2V supply voltage, the power consumption of the circuit is 11.3432 mW. The lock time of the PLL after using AFC is about 15. 258us.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98dBc/Hz. The locking range of the PLL is from 22.6GHz to 23.3GHz and the reference spur level is -69dBm that is 54dB bellow the carrier. The power consumption is 9.2mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of −94 dBc/Hz and −114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of −63 dB with the second order passive low pass filter.

This paper presents a novel combination of two fully integrated phase-locked loops (PLLs) to control the oscillation frequency and modulation frequency of a switched injection-locked oscillator (SILO). The SILO is used as an active reflector transponder in a frequency-modulated continuous wave (FMCW) radar system. A fractional-N PLL (RF-PLL) with a tri-state phase-frequency detector (TSPFD) sets the oscillation frequency of the voltage controlled oscillator (VCO) to 2.45 GHz. Another integer-N PLL (modulation PLL) switches the tail current source of the VCO to achieve SILO behavior at the time when the RF-PLL is not controlling the VCO. The RF-PLL supports division ratios from 64 to 511 with a frequency resolution of 0.2 Hz. Reference spur levels are below -48 dBc while the out-of-band phase noise is -103 dBc/Hz at a 1MHz frequency offset. The modulation PLL is based on a Maneatis-cell ring-oscillator supporting modulation frequencies between 6MHz and 20 MHz. Furthermore, the duty cycle of the modulation signal can be set in steps of 0.8 %. Due to the novel TSPFD, the oscillation frequency of the SILO changes only by 36MHz within 10 minutes when the RF-PLL is inactive. The complete circuit is manufactured in a 180nm SiGe BiCMOS process and consumes a total power of 128mW.

This article presents a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> subsampling PLL (FN-SSPLL) with a phase rotation (PR) technique. The proposed PR-based FN-SSPLL has high output frequency resolution, low phase noise, and low rms jitter. In addition, it obtains an output frequency of fractional times by dithering the phase of the signal fed back into the voltage-controlled oscillator (VCO) to increase the resolution of the output frequency by using sigma-delta modulator (SDM) on the phase-locked loop (PLL). By adopting a subsampling structure, the proposed FN-SSPLL can improve in-band phase noise by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N^{2}$ </tex-math></inline-formula> compared to standard PLLs, and the PR technique can attenuate SDM noise to improve out-of-band phase noise. The proposed PR-based FN-SSPLL was fabricated in a TSMC 65-nm RF CMOS process. The operating frequency range is 27.2–31.2 GHz and the frequency resolution is 24 Hz. Moreover, the reference frequency is 100 MHz and the phase noise is −104.67 dBc/Hz at 400-kHz offset frequency when the carrier frequency is 29.1 GHz. Finally, the measured rms jitter from 1 kHz to 10 MHz is 92 fs, the total power consumption is 23 mW, the supply voltage is 1 V, and the FoMj is −247.1 dB.

A radiation-hardened-by-design (RHBD) phase-locked loop (PLL) designed in 0.13-μm CMOS is demonstrated to effectively mitigate the single-event transient (SET) effect. In this paper, a novel Current Limiter circuit Controlled by Comparators (CLCBC) is proposed to improve SET tolerance of the Charge-Pump (CP). Further a SET tolerant Voltage-Controlled Oscillator (VCO) based on an interleaved architecture is also presented. The CLCBC features in being able to detect the abnormal current surged at the CP output node as a result of a SET strike and then to keep this abnormal current from flowing into the low pass filter (LPF) by a high resolution and fast compensation scheme. The VCO consists of a 4-stage interleaved delay buffer implemented to perform the Majority Decision Voting functions without incurring additional signal delay. Such a VCO can generate symmetric multi-phase outputs. Simulation results show that, with deposited charges of 2650fC, the output variation of the CP/ LPF hardened by the proposed CLCBC is reduced by 84.5%, in comparison to the previous work. For the RHBD PLL designed, the perturbation of the VCO control voltage is reduced by 95.6%, while the PLL recovery time is reduced by 68.9%, and the period variation range of the output is reduced by 97%, all with reference to the baseline PLL unhardened. Moreover, the jitter performance of the proposed RHBD PLL remains unaffected and is nearly the same as that of the baseline PLL unhardened.

This study presents an ultra-low-power, low-phase noise, and small-size voltage-controlled ring oscillator for use in implantable electronics operating in the Medical Implant Communication Service (MICS) frequency band and 65-nm IBM CMOS technology. This five-stage voltage-controlled ring oscillator does not require external inductor and capacitor similar to other LC oscillators, and hence, requires very small die area. A new methodology to design them has been employed in this study, and for optimizing the design of this voltage-controlled oscillator (VCO), the phase noise and power consumption of five-stage ring oscillators have been formulated and simulated for different sizes of transistors. The simulated phase noise of this VCO was -111 dBc/Hz at 1 MHz offset from a 400-MHz center frequency. The power consumption of VCO was 158 μW. This VCO has a tuning range from 352 to 454 MHz for tuning within the MICS band frequency, and frequency correction accounts for process supply voltage and temperature effects.

A low power low phase noise wide frequency range PLL

Voltage controlled oscillators (VCOs) implemented in digital VLSI IC (integrated circuit) technology typically have very poorly controlled centre frequencies and poor phase noise characteristics, thus severely limiting their use in phase locked loop (PLL) applications. The new technique presented incorporates an accurate local reference frequency into the PLL structure. The key parameters of the new PLL structure are identified and the performance characterised. It is shown that the range of frequencies to which the new PLL structure can lock can be confined to a small region around the accurate local reference frequency. It is also shown that the new PLL structure provides other benefits such as a reduction of the VCO phase noise, allowing poor quality VCOs to be used in demanding applications. The new technique does not require any monitoring nor any switching of the local frequency reference signal which is always acting.

We demonstrate the design of a novel voltage-controlled oscillator (VCO), which is based on a metal-oxide-semiconductor field-effect transistor (MOS) differential amplifier with active load. This VCO achieves low phase noise and wide tuning range. The phase noise is –120 dBc/Hz at 600 KHz offset from a 1.216 GHz carrier frequency. This value is comparable to that of a LC-based integrated oscillator. The operating frequency can be tuned from 117 MHz to 1.216 GHz with the supply voltage varying from 1.3 V to 3.3 V. Therefore, the tuning range is about 90.38% which is larger than most of the LC and ring oscillator. The VCO circuit, which is constructed using a standard 0.35 μm CMOS technology, occupies only 26.25 × 7.52 μm2 die area and dissipated 10.56 mW under a 3.3 V supply voltage.

This paper analyzes the phase noise (PN) and reference (REF) spur performance of the reference-sampling (RS) PLL when the total sampling capacitor (CS) is reduced to save the power consumption of the crystal oscillator (XO) buffer. Based on the analysis, the saved power consumption from the XO buffer can be utilized to improve the PN of the voltage-controlled oscillator (VCO), which compensates for the in-band PN degradation induced by the CS reduction. Based on this theme, we can reduce the total power consumption of the RS-PLL and the XO buffer without degrading the output root-mean-square (RMS) jitter by reducing CS if a VCO with a high figure-of-merit (FoM) and a low 1/f3 PN corner frequency is available. A type-II RS-PLL prototype utilizing a gain-boosting RS phase detector to suppress the voltage-to-current (GM) circuit noise is designed to verify the presented design strategy. With the aid of an inverse-class-F VCO with a FoM of 190.4 dBc/Hz at 1 MHz offset frequency and a 1/f3 PN corner frequency of 300 kHz across the frequency tuning range from 5.2 GHz to 6.1 GHz, the RS-PLL prototype fabricated in a 65-nm CMOS achieves low RMS jitter and REF spur of 64.8 fs and -84.1 dBc, respectively, while dissipating 6.9 mW, corresponding to a jitter-power FoM (FoMJ) of -255.4 dB.