A low power sub-harmonic injection locked 2×2 mm-wave beamforming receiver array

Microwave integrated systems in silicon provide a low cost, low power and high yield solution for wideband data communication, radar, and many other applications. Phased-array systems are capable of steering the radiation beam by electronic means, emulating the behavior of a directional antenna. This dissertation is dedicated to presenting various techniques to implement microwave integrated phased-array receivers in silicon-based technologies in the context of three design examples. A 24-GHz 0.18-µm complementary metal oxide semiconductor (CMOS) front-end was demonstrated. The front-end consists of a low noise amplifier (LNA) and a mixer. The LNA utilizes a novel topology common-gate with resistive feedthrough to obtain low-noise performance. The entire front-end achieves a 7.7dB noise figure and a 27.5dB power gain. A fully integrated 8-element 24-GHz silicon germanium (SiGe) phased array receiver was implemented. The receiver uses two-step downconversion and local oscillator (LO) phase shifting with 4-bit resolution. The signal is combined at the 4.8-GHz intermediate frequency. The 16 phases of 19.2-GHz LO signal are generated with a voltage controlled oscillator (VCO) and symmetrically distributed to the phase selectors at all path. Appropriate phase sequence is applied to the phase distribution transmission lines to minimize mismatch. An integrated frequency synthesizer locks the 19.2-GHz VCO output to a 75-MHz external reference. Measured array patterns show a peak-to-null ratio of more than 20dB and a beam steering range covering all signal incident angles. An integrated 4-element 77-GHz SiGe wideband phased-array transceiver was implemented. Two-step conversion is used at both the receiver and the transmitter. A differential phase of 52 GHz is generated by the VCO and distributed to all RF paths at the transmitter and receiver. The phase shifting is performed at the LO ports of the RF mixers using continuous analog phase shifters. The quadrature signal of the second LO frequency is generated by dividing the VCO frequency by a factor of 2 using a cross-coupled injection-locked frequency divider. The signal combining is performed at IF with an active combining amplifier. The receiver achieves a 41dB gain at 80 GHz with 3 GHz of bandwidth. The 52-GHz-to-50MHz frequency divider chain obtains 7% locking range.

In this work, the low power receiver front-end is investigated in the 865-867 MHz unlicensed band. The low noise amplifier (LNA), Mixer, local oscillator and active filter are integrated to investigate the overall performance of receiver front-end. The individual components are studied to optimize the power consumption without degrading the overall performance of receiver frontend. From the results it can be seen that for optimal power of 18mW, 2.01 dB of noise figure was attained. For integrated LNA with mixer, at optimal 48mW power, noise figure was found to be 2.84 dB. The balun circuit in the receiver was replaced by a current amplifier and performance was compared. Receiver front-end for 865-867 MHz at 60mW power with 3.3dB noise figure was obtained.

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain $$\hbox {S}_{21}$$ of $$20.10 \pm 1.65\,\hbox {dB}$$ across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, $$\hbox {S}_{11}$$ , lies below $$-\,10$$ dB from 4.9–9.1 GHz frequency. Moreover, the output reflection ( $$\hbox {S}_{22}$$ ) and reverse isolation ( $$\hbox {S}_{12}$$ ), is below $$-\,10$$ and $$-\,48$$ dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure ( $$\hbox {NF}_{min}$$ ) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of $$\pm \,0.45\,\hbox {dB}$$ in its $$\hbox {NF}_{min}$$ characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is $$-\,4.22$$ dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of $$\pm \,115\,\hbox {ps}$$ and $$\pm \,1.65\,\hbox {dB}$$ , respectively.

This paper presents the design of a low noise amplifier (LNA) with on-chip notch filters for LTE cellular applications. The on-chip notch filters act as harmonic signal attenuators thereby notching out notorious blocker components that may occur at the harmonics of the local oscillator (LO) in the operation of direct conversion receiver. Proposed LNA consists of a cascode common-source (CS) amplifier with inductor degeneration as the input stage, cascaded with another cascode common-source stage as a second stage, and an output buffer for load impedance matching. Combining the degeneration inductor with an additional capacitor at the source gives an LC notch filter operation. The input impedance is therefore modulated along with the degenerated notch impedance at the fundamental and third harmonic frequencies of the LO. Similarly, the parasitic capacitance of the CS and common-gate (CG) are resonated with the intermediate inductor between the cascode CS and CG thereby providing blocker rejections at third and fifth harmonics of the LO. The proposed LNA was designed in TSMC 40 nm CMOS process with simulation results obtained as; S21 of 33 dB, noise figure (NF) of 1.58 dB at 1.5 GHz, and S11 well below −10 dB from 1.3 - 1.71 GHz as the operational bandwidth (LTE receive bands 11, 21, 24, 32 and 45). Additionally, blocker signals occurring at $3\omega_{o}$ and $5\omega_{o}$ of the LO were rejected by −83 dBc and −98 dBc respectively while consuming only 9 mA DC bias current from a 1.2 V supply.

A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based gm-boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.

A novel circuit structure of a common-gate single-stage low-noise amplifier (LNA) has been proposed in this work. The LNA has been designed for Ku-Band (12 to 18 GHz) applications using the TSMC 0.18-µm CMOS process. New analytical expressions have been derived for the noise factor of a common-gate LNA. A minimum noise figure (NF) of 4.86 dB and a maximum S 21 of 10.55 dB has been obtained for the design. The circuit displays a high linearity with an IIP3 value equal to 12 dBm and P 1-dB value equal to −3 dBm at the mid-band. Detailed input and output matching networks have been designed to maintain a low NF and a high gain across the band. The LNA operates from a 1.8 V supply and consumes a current of 5.56 mA excluding the output buffer.

A 20–29 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with excellent input return loss (S11), flat and high power gain (S21), and flat and low noise figure (NF) is demonstrated. Wideband input impedance matching was achieved by using the proposed T-match input network to generate two S11 dips. Flat and high S21 was achieved because the inductive-peaking second stage and the current-reused final two stages can compensate the gain degradation of the source-degenerative first stage at medium and high frequencies, respectively. Flat and low NF was achieved by adopting a slightly under-damped Q-factor for the second-order NF frequency response. The LNA consumed 22.07 mW and achieved S11 of −15.5 to −26.8 dB, S21 of 16.2±2.5 dB, minimum NF (NFmin) of 3.1 dB (at 20 GHz), and an average NF of 3.6 dB over the 20–29 GHz band of interest, one of the best reported average NF performances for a 24 GHz band CMOS LNA with bandwidth wider than 6 GHz in the literature.

A novel sub-harmonic injection-locked balanced oscillator is proposed. The circuit provides two outputs with a 180° phase difference by employing a transmission line section for impedance transformation to meet the oscillation conditions. A coupling network is connected at the mid-point of the transmission line to inject the sub-harmonic frequency. This eliminates the need for a circulator or balun. The circuit is small and consumes low DC power. Under the locking state, the circuit provides double the injection frequency and also the phase noise of the two outputs is substantially improved.

In this paper, 28 GHz millimeter wave (mmWave) low noise amplifier (LNA) and a down converter for 5G is designed using 65 nm CMOS technology. This design is used with a standard radio receiver chain and each block is tuned to its best performance to obtain the necessary overall specifications. Typical single-stage common source (CS) cascode with degenerative inductor topology is used for LNA to meet high gain requirement. The designed LNA has a peak gain of 16.43 dB, noise figure (NF) of 3.6 dB, good linearity (P1dB of 10 dBm) and −3 dB bandwidth of 2.2 GHz. A modified Gilbert cell topology is used for down converter which gives a conversion gain of −2.2 dB from 27.5 to 29.5 GHz frequency, third-order intercept point IIP3 of 10 dB at 28 GHz from a 1.5 V supply voltage and a 1 Vpp of local oscillator (LO) drive. With the proposed LNA and down converter, a direct conversion receiver is analyzed. Cascaded gain of 39 dB, NF of 4.2 dB, third-order intercept of −23.3 dBm and a low error vector magnitude (EVM) of −37.76 dB is observed for 64 QAM with a received power of −100 dBm for the receiver.

An analytical expression for the minimum achievable noise figure for a specified gain at a given frequency is derived for a microwave amplifier. The minimum noise figure is given in terms of the specified gain, the amplifier noise parameters, and the S-parameters. Similarly, another expression for the maximum gain at a specified noise figure is derived in terms of the noise figure, the noise parameters, and the S-parameters. It is shown that these expressions simplify the tradeoff considerations for broadband low noise amplifier design by avoiding the need to draw several constant noise and gain circles at each frequency of interest. >

A design flow to explore the design parameters space of integrated inductively-degenerated low noise amplifiers (LNA), under the constraint of matched input impedance, is presented. It is based on standard circuit simulation tools and can be easily automated. The method is applied to the design of a 5.5 GHz 0.18 /spl mu/m CMOS LNA with minimum noise figure (NF) for a fixed bias current. The measured NF of 2.6 dB, with input reflection coefficient lower than -15 dB at 5 mA bias current, shows good agreement with simulations.

This paper presents a 94GHz 2×2 phased-array frequency-modulated continuous wave (FMCW) imaging radar transceiver. The transceiver consists of two receiving paths, two transmitting paths and a local oscillator (LO) generation path. In order to improve gain and noise performance, multi-paralleled transistors with small number-of-fingers are used to design power amplifier (PA) and low noise amplifier (LNA). A 24GHz voltage-controlled oscillator (VCO) is used to generate wideband FMCW signals, and two differential push-push cascode doublers are used to act as a quadrupler, which has a low power and high stability. Phase shifter (PS) with constant insertion loss (IL) compensation is used to achieve constant gain among different phase states. The LO path has a continuous frequency tuning range of 14GHz. The transmitter has a maximum output power of 11 dBm and 2.8dB power flatness over 14GHz bandwidth. The receiver has a conversion gain of 20dB and a noise figure (NF) of 10.5dB.

This article presents a 48–56 GHz mixer-first fourth-harmonic sub-sampling eight-path-filter receiver integrating an on-chip differential dipole antenna, a six-port hybrid coupler, and an eight-phase 12.5-duty-cycle local oscillator (LO) generator with phase and duty-cycle calibration. A sub-sampling gapped eight-path-filter configuration is proposed to relax LO operating frequency and rise/fall time requirements so that LO power consumption can be reduced significantly. An on-chip antenna (OCA) employs crossed artificial-magnetic-conductor patterns to improve its power gain. A six-port transformer-based quadrature hybrid coupler is employed for both input matching and radio frequency (RF) quadrature signal generation. Fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 28 nm CMOS technology, the receiver prototype achieves a peak gain of 17.3 dB, a minimum noise figure (NF) of 14.7 dB, IP1dB of −12 dBm, a peak in-band IIP3 of +4.0 dBm, an out-of-band (OOB)-B1dB of +0.8 dBm, and >1 dBm HB1dB while consuming 80.2–99.7 mW. With the OCA, the receiver system achieves a peak gain of 11 dB, demonstrating a maximum 3.6 Gb/s data rate at an air distance of 25 cm.

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

A low-noise amplifier (LNA) employing novel self-biased shunt-feedback mechanism for X band applications is presented. The shunt-shunt feedback impedance is not only used to eliminate the use of gate-biased voltage, but also neutralize the miller capacitor of the input transistor. With combining current-reused technique into the amplifier, it is benefit to boost power gain and maintain low power consumption. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability across the required bandwidth. A prototype was fabricated in 0.18-µm CMOS process to demonstrate the proposed LNA architecture. The measurements show that a maximum power gain of 10 dB, a minimum noise figure (NF) of 4.5 dB, −6 dBm input-referred third-order intercept point (IIP 3 ), and drawing 7.6 mA from a 1.8-V supply.