A low-power variable length decoder based on successive decoding of shoft codewords

In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 mum process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.

A new hybrid coding technique is introduced which is based on the Discrete Cosine Transform, interframe DPCM, conditional replenishment, detection of significant subareas in the transform domain, adaptive quantization, adaptive Huffman coding and postbuffer control. This coder concept is the result of a comparison of several coding methods including uniform/nonuniform quantization, constant/variable word length coding and prebuffer/post-buffer control schemes. An important feature of the presented coder is the selection of transform coefficients within each block which are grouped in subareas for adaptive entropy coding. The components of the coder are described and its excellent performance is demonstrated by means of SNR-measurements and a typical videoconference sequence.

Context-based adaptive variable length coding (CAVLC) is a new and efficient entropy coding tool in H.264/AVC (advanced video coding). This study proposes a low-power and cost-effective CAVLC decoding architecture for the H.264/AVC baseline profile. Specifically, this study proposes an optimum two-layer power model for the variable length look-up table (VLUT) in the CAVLC decoder, and divides the decoding phase of the LUT into two-layer decoding to reduce power consumption. To achieve a cost-effective design, the proposed design merges common codewords to reduce the hardware cost among different LUTs in the second layer decoding. The proposed decoder is based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm CMOS technology, and was completely verified on a field-programmable gate array (FPGA) emulation platform. The proposed design meets the demands of the real-time CAVLC decoding and reduces power consumption by 44-48% more than previous low-power CAVLD schemes. Finally, the proposed low-power and cost-effective CAVLD design is suitable for H.264/AVC portable applications.

HDTV CODEC for Digital Recording

An architecture is described for performing addition and subtraction of numbers in the logarithmic number system using small lookup tables. Previous implementations require approximately 4*2/sup F/ words for F bits of precision in the fraction. The author shows how to reduce the size of the lookup table to fewer than (18+F)*2/sup F/2/ words. The key to this is the use of a linear approximation of the nonlinear functions stored in the lookup tables. The functions involved are highly nonlinear in some regions, so variable size regions are used for the approximation. The replacement of the F exponential dependence on the number of words by F/2 allows roughly 50% more bits of fractional precision to be obtained for a given amount of ROM. The architecture is mathematically analyzed, yielding explicit expressions for all design parameters. The approach is illustrated with an example logarithmic addition and subtraction unit using 32-b words with 30-b exponents containing 22 fractional bits. A factor of 118 reduction in table size compared to previous techniques is achieved for this example. >

In this paper, we propose a unified architecture for computation of double-precision floating-point division, reciprocal, square root, inverse square root and multiplication with a significant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modified Goldschmidt algorithm to achieve better area efficiency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the final accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a reconfigurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is finally implemented and synthesized in SMIC 0.13-μm CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area efficiency (performance/area ratio) of the proposed unified architecture is increased by about 20% in average, which is a better performance-area trade-off for embedded microprocessors.

Let M be a submonoid of the free monoid A *, and let X⊂ M be a (variable length) code. X is weakly M-complete iff any word in M is a factor of some word in X * [NS 03]. In this paper, we are interested by an effective computation of a weakly M-complete code containing X. Given a regular submonoid and given a code X⊂ M, we present a method of completion which preserves the regularity of X.KeywordsWordsfree monoidsubmonoidcodeautomatoncompletenessdensity

In this thesis we propose a new, biologically inspired, paradigm for the design of high speed communication systems. The paradigm consists of a new modulation format referred to as Interval Modulation (IM). In order to transmit data in an efficient manner using this format, new coding techniques are needed. In this thesis we propose a coding technique based on variable length to variable length prefix trees and code construction algorithms are outlined. These codes are referred to as Interval Modulation Codes (IMC). Furthermore, data encoded with this modulation format cannot be transmitted or received using conventional synchronous CDR based receivers. In this thesis we outline a new asynchronous circuit architecture for both the transmitter and receiver. The architecture is based on active delay lines and eliminates the need for clock recovery.

A major task in processing scanned images is converting the color values from the non-colorimetric color space used by the scanner to a device-independent color space or the color space of an output device. For example, typical color scanners produce 24-bit RGB values for each color pixel, while most printers use color spaces such as CMY or CMYK. While this conversion can be accomplished using a lookup table, the 16 million entries required makes the direct lookup table prohibitively large. This suggests use of a sparse lookup table, where only certain values are directly mapped. For all color values that are not directly mapped, the unknown values may be calculated from the nearest table entries via trilinear interpolation, a computationally intensive process. This paper presents a method of efficiently converting from a set of noisy color values to a set of device colorants. Using a deterministic process, 24-bit scanned color values are reduced to dithered 12-bit RGB table indices. After the reduction, a small but complete lookup table with 4096 entries converts the RGB values directly to the output color space. This stochastic interpolation process, while minimizing banding and abrupt color transitions, eliminates the need for trilinear interpolation of the data and significantly reduces the size of the lookup table.

In this paper, a novel dynamic addressing scheme for wireless sensor networks (WSNs) is proposed by using variable length coding. A WSN is typically composed of numerous tiny energy-constrained sensor nodes with limited information processing and data storage capabilities; thus, the energy-efficient strategy is the key issue in designing protocols for WSN. Traditional addressing strategies adopt flat addressing (static and uniform addresses) for sensor nodes. However, the proposed variable length dynamic addressing (VLDA) for sensor nodes is based on the fact that different nodes in the network have uneven traffic loads. Therefore, nodes with more data to receive or send are allocated with shorter addresses. Whether a node is busy or not is determined by the network traffic distribution (NTD), which is defined as the number of data packets each node has received or sent in a period of time. Sensor nodes’ energy is saved by VLDA scheme; hence, the wireless sensor network’s lifetime is extended. In the simulation, a 20% improvement has been achieved through the addressing scheme compared to traditional flat addressing.

Design of cryptographic applications need special care. For instance, physical attacks like Side-Channel Analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AES. SCA considers the "leakage" of a well chosen intermediate variable correlated with the secret. Field programmable gate-arrays (FPGA) are often used for hardware implementations for low to medium volume productions or when flexibility is needed. They offer many possibilities for the computation, like small Look-Up Tables (LUT) and embedded block memories (BRAM). Certain countermeasures can be deployed, like dual-rail logic or masking, to resist SCA on FPGA. However to design an effective countermeasure, it is of prime importance for a designer to know the main leakage sources of the device. In this article, we analyze the leakage source of a Xilinx Virtex V FPGA by studying 3 different AES architectures. The analysis is based on real measurements by using specific leakage models of the sensitive variable, adapted to each architecture. Our results demonstrate that, BRAM which were considered to leak less traditionally, are found to be equally vulnerable if we change the attack target from address register to output latch. Hence by providing important clues about the leakage, this study allows the designers to enhance the robustness of their implementation in FPGA.

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.

Due to the rapid development of communication systems, a highly flexible scheme of multi-rate multi-length channel code is urgently required. In this paper, we propose a design method of highly flexible rate-compatible (RC) length-scalable (LS) low density parity check (LDPC) codes, which is based on the progressive extension idea of both information bit/node and parity check bit/node. According to our method, a family of RC-LS-LDPC codes with one common template matrix can be generated, which facilitates hardware implementation. With the aid of multi-edge type density evolution (MET-DE) analysis, the method can achieve near-capacity performance for each code rate and code length. The simulation results show that the designed codes with arbitrary rate and variable code length are within 0.30dB to 0.48dB compared with Shannon limit at bit error rate (BER) =2∗10−9 under BI-AWGN channel.

When variable length codes are used in the presence of error, slippage can occur. The number of symbols decoded before synchronization is regained can differ from the number of encoded symbols, causing misinterpretation of data. In previous work certain synchronization schemes have been shown to be satisfactory in preventing permanent loss of synchronization and slippage in the presence of random error. In this paper we demonstrate that these schemes can also be satisfactory in the presence of burst errors, and that their relative merits remain the same.

FPGAs (field programmable gate arrays) need not be limited to a single fixed-size truth table in each block. The authors discuss the utility of allowing each block's single large table (e.g. one 5-input, 32-b table) to be reconfigured into smaller tables (e.g. eight 4-b tables). Results describing the efficiency of packing some standard benchmark circuits into various configurations are presented and the cost/benefits discussed. It is shown that a logic block containing four lookup tables, each of which is 8-b RAM, is the best choice if only the area efficiency is considered. It is also shown that if circuit speed is considered, a logic block containing two lookup tables, each of which contains 16 b of RAM, is the best choice. >