A low-voltage CMOS current-mode differential front-end for optical communications

Low-voltage subthreshold CMOS current mode circuits: Design and applications

This paper presents a new low-voltage fully differential CMOS current-mode preamplifier for GBps data communications. The number of transistors between the power and ground rails is only two so that the minimum supply voltage is one threshold voltage plus one pinch-off voltage. The preamplifier is a balanced two-stage configuration such that the effect of bias-dependent mismatches is minimized. A new inductive series-peaking technique is introduced to increase the bandwidth by utilizing the resonance characteristics of LC networks. In addition, a new negative differential current feedback technique is proposed to boost the bandwidth and to reduce the value of peaking inductors. The preamplifier has been implemented in TSMC 0.18 ?m, 1.8 V, 6-metal mixed-mode CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3 pF photodiode capacitance, simulation results demonstrate that the preamplifier has bandwidth of 3.5 GHz and provides a transimpedance gain of 66 dB?. The total chip area is approximately 1 mm2 and the DC power consumption is about 85 mW.

Logic gates serve as the fundamental building blocks of digital circuits, and among them, the XOR (exclusive OR) gate stands out due to its unique properties. The XOR gate outputs true only when the number of true inputs is odd, making it a pivotal element in various applications, especially in the realm of machine learning and AI development. Korean studies at the intersection of digital logic and recreational mathematics have demonstrated how XOR gate principles provide an effective framework for algorithmically solving the Lights Out game. Comparative research conducted in Korea indicates that the puzzle-solving mechanics of the Lights Out game can be effectively analyzed using the same principles that govern XOR gate behavior in digital circuits. We explore how linear algebra can be used to analyze the Lights Out game. The XOR gate can also be used in AI development in several contexts, particularly in areas that involve binary decision-making, error detection, and encryption/decryption. Simple computations, reversibility, symmetry, and inversion are some of the useful properties of the XOR gate, which make the XOR gate versatile, popular, and applicable across all binary data.

Organic electronic circuits based on organic electrochemical transistors (OECTs) are attracting great attention due to their printability, flexibility, and low voltage operation. Inverters are the building blocks of digital logic circuits (e.g., NAND gates) and analog circuits (e.g., amplifiers). However, utilizing OECTs in electronic logic circuits is challenging due to the resulting low voltage gain and low output voltage levels. Hence, inverters capable of operating at relatively low supply voltages, yet offering high voltage gain and larger output voltage windows than the respective input voltage window are desired. Herein, inverters realized from poly(3,4‐ethylenedioxythiophene):polystyrene sulfonate‐based OECTs are designed and explored, resulting in logic inverters exhibiting high voltage gains, enlarged output voltage windows, and tunable switching points. The inverter designs are based on multiple screen‐printed OECTs and a resistor ladder, where one OECT is the driving transistor while one or two additional OECTs are used as variable resistors in the resistor ladder. The inverters’ performances are investigated in terms of voltage gain, output voltage levels, and switching point. Inverters, operating at +/−2.5 V supply voltage and an input voltage window of 1 V, that can achieve an output voltage window with ∼110% increment and a voltage gain up to 42 are demonstrated.

A methodology for automated synthesis of mixed analog/digital hardware architectures for Artificial Neural Network (ANN) applications is presented, The ANN system is input in the form of a Data Flow Graph (DFG) of operators. The output is a high-level interconnection description of mixed analog/digital building block circuits that is generated by searching a multidimensional design space to satisfy the throughput requirements and minimize an area-time cost function. A combination of quantitative analysis and behavioral modeling techniques tackles the problems of hardware nonidealities by screening suitable analog circuits. Digital hardware is employed when no analog circuit is found that satisfies the performance requirements of any operation. A heuristic partitioning scheme reduces the interfaces between blocks of circuits operating in analog and digital modes. The parallelism in ANN systems is, handled by a new scheduling and allocating procedure that selectively sequentializes groups of operations with the goal of iteratively improving an area-time cost function. The synthesizer is also capable of embedding hardware units that are intended to operate asynchronously. The synthesis methodology is illustrated with two design examples.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Introduction MoS2 is a next-generation 2D material which is considered for applications in digital electronics [1–3]. Although enormous progress has been made in the area of MoS2 FETs, the available prototypes do not yet meet the high expectations. Commonly known reliability issues like the frequently observed hysteresis in the ID(VG) characteristics [4–6] and the large drifts of the threshold voltage over time [7] prohibit stable device operation for this technology. Apart from fabrication related issues, these performance limiting issues are the most critical obstacles inhibiting industrial applications of MoS2 FETs. Complementing our previous works [7–9], here we present a physical modeling approach for studying the charging and discharging of preexisting defects in the surrounding dielectrics. Devices We compare the hysteresis widths measured at the gates of MoS2 based FET devices at different sweep frequencies. Additionally, we study the drifts of the threshold voltage on these devices in a systematic way by evaluating the threshold voltage shifts observed after stressing the devices for different time spans and stress voltages. From the wide range of samples available, we choose devices using a thermal SiO2 layer as a back-gate dielectric. The MoS2 is either exposed to the ambient or covered by an amorphous Al2O3 layer. This thin dielectric layer enables a top gate contact and is at the same time necessary to prevent any degradation of the device characteristics due to the impact of the ambient [4,8]. Degradation Modeling For simulating the transfer characteristics we use a TCAD device simulator solving the drift-diffusion equations [10]. This approach is valid for devices with large dimensions and a large number of scattering centers, even if 2D channel materials are used [11]. The impact of interface defects is considered by using the standard SRH model. The transient charging and discharging of oxide defects leading to the hysteresis and the long-term drifts of the threshold voltage are described using the four-state NMP model [12,13]. The physical defect properties determining the degradation, such as trap positions and energy levels, depend on the respective oxide and have been studied in detail for SiO2 [8,14] and Al2O3 [9]. Results In accordance with our previous experimental work [7], we argue here that the common cause for the hysteresis in the ID(VG) and the observed long-term drifts are charge capture and emission events in the surrounding dielectrics. Even though several groups claim that the hysteresis is due to charge trapping at the interface [6,15,16], we argue here that interface traps can only impact the threshold voltage via a change in the sub-threshold slope. An observed hysteresis provides information about fast-switching oxide traps, while the systematic stress measurements reveal details about slow-switching oxide traps. One important quantity, necessary for understanding the size of the observed threshold voltage shifts, is the band alignment of the defect bands in the dielectrics with respect to the band edges of the semiconductors, illustrated in Fig. 1. Conclusions We use a drift-diffusion based simulation methodology to describe the cause of the threshold voltage drifts observed in the ID(VG) characteristics of MoS2 FETs, namely the charge capture and emission processes in the gate oxide traps. Thus, it is of utmost importance not only to investigate the fabrication of 2D layers, but also to focus on the quality and the defect bands of amorphous dielectrics to enable further progress in the area of FETs based on 2D materials. Acknowledgments The authors gratefully acknowledge financial support through FWF grant noI2606-N30.

FAILURE mechanisms at surfaces and interfaces in thin film structures have been studied in thin film field effect triodes. These triodes are very suitable for the study of failures at semiconductor-insulator interfaces as the electrical characteristics strongly depend on the state of this interface. The thin film triodes have been subjected to humidity, to elevated temperature, and electrical stress. During the stress tests the failure of the main materials parameters in these devices has been studied as a function of time and stress. The main failure was a change of the threshold or pinch-off voltage in these devices, indicating that the surface potential of the semiconductor changed under stress. The field effect mobility in the semiconductor was rather constant. The capacitance decreased slightly at elevated temperatures and under electrical stress. The rate equation describing the change of the threshold voltage at elevated temperatures could be explained by assuming a desorption process. Experimentally it could be shown that water contributes to this effect. The failure of thin film field effect triodes under electrical stress was more complex. The main cause of failure appeared to be the electrical field between the gate electrode and the semiconductor. A tentative model for the failure mechanisms under electrical stress is presented which is based on a correlation of the observed failure modes to the slow relaxation characteristics of the semiconductor surface conductivity. It was discovered that the experimental devices could be classified in two types which show a distinctly different slow relaxation behavior.

Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V/sub Goff/ is studied. It is shown that when V/sub Goff/ is around the threshold voltage (pinchoff voltage) V/sub th/, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V/sub Goff/ is much more negative than V/sub th/.

Pipelined architectures enable the implementation of high-speed, high-resolution, low-power analog-to-digital converters (ADCs). Concurrent processing of analog signals results in power and/or speed advantages over flash and multistep ADC architectures. While self-calibration techniques reduce the effects of component mismatches, the digital crosstalk due to correction circuitry can degrade the noise and linearity performance of the overall converter. Previous pipeline ADCs achieve high speed and high resolution, but with the digital circuitry off chip. This 16 b 1 MSample/s pipeline ADC with on-chip digital correction circuitry operates on a single SV analog supply. Problems due to digital crosstalk and solutions reducing its effects are presented. Reduction of integral non-linearity (INL) errors due to capacitor voltage coefficient are discussed.

As essential building blocks of sequential digital circuits, optimizing the power consumption of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper proposes an ultra-low power 25-transistor (29-T with reset function) true single-phase clocked (TSPC) flip-flop by eliminating all redundant charges and discharges. Floating nodes are compensated by transistor-level optimization, which also enables a fully static and contention-free FF circuit design. The proposed FF is implemented in 55 nm CMOS technology. Post-layout simulation results demonstrate that at a supply voltage of 0.6 V and 10% data activity, the proposed circuit consumes only 0.153 fJ/cycle.

The design and optimization of high-speed integrated bipolar circuits requires accurate and physical transistor models. For this, an improved version of the compact model HICUM was developed. It is an extension of the small-signal model recently described to the large-signal (transient) case. The model, which takes into account emitter periphery and non-quasi-static (NQS) effects, is semi-physical, allowing the calculation of its elements for arbitrary transistor geometries from specific electrical and technological data. This is an important precondition for transistor optimization in a circuit and for worst case analysis. The model was verified for basic building blocks of high-speed digital circuits like emitter follower and current switch. For this, mixed-mode device/circuit simulation is used instead of measurements, since the latter would give too large errors for the fast transients of interest. It is demonstrated that-in contrast to the obsolete but frequently used SPICE Gummel/Poon model-the new HICUM is well suited for modeling very-high-speed transistor operation also at high current densities. Moreover, it is shown that at very fast transients the influence of NQS effects can no longer be neglected. As a practical application example, a high-speed E/sup 2/CL circuit is simulated using the new model. The results show again that high-current models are very useful for designing IC's at maximum operating speed. This is because the optimum emitter size is often the minimum size, which is limited by high-current effects. Especially, in the case of current spikes (e.g., in emitter followers) it is difficult to find the optimum emitter size without having adequate transistor models. >

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

In this paper, it is shown that the output impedance of an inverter can be designed to be capacitive via the feedback of the filter inductor current through an integrator. Such inverters are called C-inverters (inverters with inductive and resistive output impedances are called L-inverters and R-inverters, respectively). Moreover, a recently-proposed robust droop controller is further developed and applied to inverters with capacitive output impedances to achieve accurate sharing of real power and reactive power and to maintain the output voltage within the desired range. Simulation results are provided to demonstrate the feasibility and the performance. Under the same conditions, simulation results show that an inverter achieves lower total harmonic distortion (THD) when it is designed to have a capacitive output impedance than when it is designed to have a resistive or inductive output impedance.

A new current-mode, low-power, low-voltage and high-speed CMOS sample-and-hold circuit has been designed and fabricated. A new current-mode differential switching scheme has been adopted to eliminate errors caused by feedthrough injection from the sample switches. The experimental result yields 9-bit resolution in 9 mW power dissipation, in a 20 MHz clock frequency from a 3 V power supply.

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates