Low-voltage subthreshold CMOS current mode circuits: Design and applications

This thesis deals with the design of a low-voltage fully-differential CMOS current-mode preamplifier for optical communications. An in-depth comparative analysis of the building blocks of low-voltage CMOS current-mode circuits is carried out. Two new bandwidth enhancement techniques, namely inductor series-peaking and current feedback, are introduced and implemented in the design. The feedback also reduces the value of the series-peaking inductor. The minimum supply voltage of the amplifier is only one threshold voltage plus one pinch-off voltage. The preamplifier has a balanced differential topology such that the effect of bias dependent mismatches is minimized and the amplifier is insensitive to the switching noise caused by the digital circuitry. Negative differential current feedbacks are implemented to boost the bandwidth and increase the dynamic range.

The design of low power and low voltage analog circuits is truly challenging. Therefore different approaches have been proposed and successfully employed. In this paper some of the low voltage topologies like Bulk Driven, Self-Cascode and DTMOS have been presented, and issues related to design are discussed briefly. These topologies are also used to design second generation current conveyors (CCII) and voltage mplifiers. The CCII is an important building block of a current feedback circuit like a current feedback operational amplifier (CFOA). Low voltage and low power are needed when those circuits are employed in the biomedical application and portable equipment. The designs are implemented using 0.18 µm CMOS technology.

In this paper, a frequency analysis of a voltage feedback amplifier based on second generation current conveyors with inductive input/output impedance, is presented. The traditional voltage amplifier configured from voltage and current feedback operational amplifiers are studies and compared. PSPICE simulation confirms the theoretical approach.

In this paper, two low component count Voltage Mode (VM) and Current Mode (CM) higher order filters are proposed. The higher order filters are derived from second order filter module, which are realised by using Second Generation Current Conveyors (CCII). Both the filter modules have low component count and lower sensitivity figure. Apart from this, both the modules provide the feature of cascadability, which is required for realisation of higher order filter function. Performances of all the proposed circuits are verified by PSPICE simulation using TSMC 0.25μm technology parameters.

The quaternary full adder accepts two quaternary inputs and a binary CARRY input and develops a two-quaternary-digit output word that is the base-four sum of the inputs. A current-mode CMOS circuit is presented that implements the quaternary threshold logic full adder function more area efficiently, with fewer current comparators and decoders (and hence transistors), than previously reported. It has been realized in standard polysilicon-gate CMOS technology.

The influence of crystallinity on the resistive switching behavior of TiO 2

A current mirror circuit is widely utilized as an important building block in analogue signal processing circuits. This paper describes a high-precision low voltage bipolar current mirror circuit. Well known current mirror circuits, such as a simple current mirror and a Wilson current mirror, have a trade-off between low-voltage operation and accuracy of the current gain. The accuracy of the proposed current mirror is high in spite of low current amplification factor (β) of transistors and large current output (or a large number of the multiple output). The current mirror circuit can operate at a 1V or less supply voltage. The high accuracy is realized by negative current feedback with high gain. Thus, the stability of the circuit and compensation methods are discussed. PSPICE simulation shows that the proposed current mirror circuit compensated using Miller components composed of a capacitor and a resistor is stable and can operate at a 1V supply voltage.

A simple circuit design technique for the realization of compact low-voltage low-power CMOS four-quadrant analog current multiplier circuit has been suggested. It is based on the use of the square-law characteristic in the NMOS current squaring function circuit operating in the saturation region. The suggested four-quadrant current multiplier circuit is designed for implementing in TSMC 0.25-μm CMOS technology with a low supply voltage of ±0.75V. To evaluate the circuit performance, the circuit has been simulated by PSPICE program. The simulation results show that the circuit has a linearity error of about 1%, a THD of 1.07% at 100 kHz, the total power consumption of 87.6 μW and -3dB bandwidth of 1.32 GHz.

The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

This paper introduces a CMOS operational amplifier with constant transconductance, suitable for operation in low voltage environments. A constant transconductance is ensured for the whole common mode input stage which is based on flipped differential pairs. The proposed operational amplifier is designed to operate with a 1-V supply and is implemented in 0.18-μm standard CMOS technology. The results show that a closed-loop unity-gain bandwidth achieves 7.6 MHz and an open-loop low-frequency gain is higher than 73 dB with a 1-MΩ‖15-pF load.

A five-port general purpose analogue building block, termed as an operational floating current conveyor (OFCC), is described. The OFCC combines the features of a current feedback (CFB) operational amplifier, second generation current conveyor and operational floating conveyor (OFC). A simple implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working model. The OFCC is then used as a single block to realize the current conveyors (CCII+ and CCII-). Experimental results are presented and show good behavioral agreement with simulation results.

A new five-port general purpose analogue building block, termed as an operational floating current conveyor (OFCC), is described. The OFCC combines the features of current feedback (CFB) operational amplifier, second generation current conveyor and operational floating conveyor (OFC). A simple implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working model. The OFCC is then used as a single block to realize the four main amplifier types and the current conveyors (CCII+ and CCII-). Computer simulation results are presented and discussed. >

A FGMTL (FGMOS Translinear) principle based current mode one quadrant squarer/divider circuit operating at low voltage in saturation region is presented. Squarer/divider is the key circuit which acts as a core building block for nonlinear signal processing functions. Low voltage square/divider can be constructed using FGMTL principle in place of MTL (MOS Translinear) principle in saturation. Multi-input nature of FGMOS transistor reduces the transistor’s threshold voltage which allows low voltage operation of the proposed circuit in saturation region. Proposed circuit is designed at a supply voltage of 0. 7V. It offers a bandwidth of 0. 5GHz when simulated in LTSPICE software using 0.18$\mu$m CMOS technology. THD of 2.3% to 4.7% is obtained for the sinusoidal peak to peak input current range from 1$\mu$A to 10$\mu$A at a frequency of 1KHz.

This paper introduces a new simple Schmitt trigger circuit using a plus-type differential voltage-current conveyor (DVCC+) and only two grounded resistors. The proposed circuit is very simple and enjoys adjustable lower and higher threshold voltages as well as the output saturation levels. The application of the proposed Schmitt trigger circuit to the square/triangular wave generator is also given. Moreover, a current feedback operational amplifier (CFOA)-based square/triangular wave generator is derived from the proposed DVCC+-based circuit. Simulation and experimental results are presented to exhibit the performance of the proposed circuits.

In order to install a chaotic neural network to solve the traveling salesman problem (TSP) on an integrated circuit, a chaotic neuron circuit is designed by using a current mode circuit. First, the characteristics of the output function of the neuron circuit are determined by numerical simulation so that they have excellent capability to solve the TSP. Next, the network is designed such that the chaotic neural network consisting of the designed neuron circuits can seek the optimum solution efficiently. Further, a circuit is proposed which realizes chaotic annealing in order to improve the convergence of the chaotic neural network. The ability of the proposed network using the annealing circuit to derive an optimum solution of the TSP is studied. From the simulation results, it is confirmed that the proposed chaotic neuron circuit is suitable for integration of the chaotic neural network to solve the TSP. © 1999 Scripta Technica, Electron Comm Jpn Pt 3, 82(9): 52–62, 1999