A method for automatic design error location and correction in combinational logic circuits

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Y}_{{2}}\text{O}_{{3}}$ </tex-math></inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Given two circuits, one specification and the other design, a correspondence between states of the two circuits is first assumed or the circuits are expanded by several time frames. Based on that correspondence or expansion, the proposed methods try to automatically correct design errors by changing the part of the circuit which is specified by a designer. Experimental results show that the proposed method can be a very effective tool for FSM designs where small manual design modifications may happen frequently.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The evaluation of an automatic grammatical error correction system is an important content in the field of automatic grammatical error correction. This paper summarizes the technical routes of the four most representative evaluation metrics of the automatic grammatical error correction systems. Firstly, it introduces the characteristics and composition of each metric, then summarizes its defects, and finally puts forward some suggestions for the future development of the metrics. This paper holds that the application of natural language processing technology should be strengthened in the future development of evaluation metrics.

Comet — A new method for the deterministic test pattern generation in c-circuits

This paper proposes a method for detecting delay faults of gates in a combinational logic circuit. Assuming that a gate of the circuit has a small delay (a unit delay), the generation of a test for the circuit is described. This paper also describes the generation of the timed seven-valued calculus used in the method. The method has been applied successfully to benchmark circuits having unit delay and a fanout weighted delay. The experimental results show that the method has high fault coverage in all the circuits, and that this can be applied to the detection of gross delay faults. The proposed test method is called the ‘SD test’. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(6): 68–76, 1997

A sizing and constrained optimization algorithm for CMOS (complementary metal-oxide semiconductor) combinational logic circuits is presented. A constrained optimization problem is first transformed to a Lagrange multiplier form with a suitable cost function. Various techniques are applied to choose optimization variables, initial guess, and optimization direction and to reduce the occurrence of local minimum. As an example, the algorithm is applied to the minimization of power dissipation with a fixed delay constraint for the sizing of CMOS (complementary metal-oxide semiconductor) combinational logic circuits. It is shown that due to the proper choice of optimization variables, initial guess values, and optimization directions and the reduced occurrence of local minimum in the algorithm, the efficiency of the sizing and optimization are improved. The algorithm can be applied to many other circuit optimization problems with constraints.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Objective: To study the specificities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.

After using side-channel information leaked by the FPGA chip which is embedded with a block cipher algorithm, there is a scheme called improved combinational side-channel attack. This scheme mainly aimed at logical circuits implemented in S-box in background of power consumption attack and we make a level of models by power consumption in combinational logic circuits which is engendered by glitches different from traditional sequential logical circuits which is engendered by flip in the output of register with the Hamming model. In addition, we take advantage of match algorithm in a linear model and in multivariate Gaussian model from template attack to process an important data twice and the key would be recovered. At last, we make a comparison between Hamming model and our model. And prove that this paper improved the attacking efficiency and accuracy and also provided a clue to the security cipher chip from countermeasures.

Automatic cell segmentation and tracking enables to gain quantitative insights into the processes driving cell migration. To investigate new data with minimal manual effort, cell tracking algorithms should be easy to apply and reduce manual curation time by providing automatic correction of segmentation errors. Current cell tracking algorithms, however, are either easy to apply to new data sets but lack automatic segmentation error correction, or have a vast set of parameters that needs either manual tuning or annotated data for parameter tuning. In this work, we propose a tracking algorithm with only few manually tunable parameters and automatic segmentation error correction. Moreover, no training data is needed. We compare the performance of our approach to three well-performing tracking algorithms from the Cell Tracking Challenge on data sets with simulated, degraded segmentation—including false negatives, over- and under-segmentation errors. Our tracking algorithm can correct false negatives, over- and under-segmentation errors as well as a mixture of the aforementioned segmentation errors. On data sets with under-segmentation errors or a mixture of segmentation errors our approach performs best. Moreover, without requiring additional manual tuning, our approach ranks several times in the top 3 on the 6th edition of the Cell Tracking Challenge.

In this paper, we extend our previous work on deformable image registration to inhomogenous tissues. Inhomogenous tissues include the tissues with embedded tumors, which is common in clinical applications. It is a very challenging task since the registration method that works for homogenous tissues may not work well with inhomogenous tissues. The maximum error normally occurs in the regions with tumors and often exceeds the acceptable error threshold. In this paper, we propose a new error correction method with adaptive weighting to reduce the maximum registration error. Our previous fast deformable registration method is used in the inner loop. We have also proposed a new evaluation metric average error of deformation field (AEDF) to evaluate the registration accuracy in regions between vessels and bifurcation points. We have validated the proposed method using liver MR images from human subjects. AEDF results show that the proposed method can greatly reduce the maximum registration errors when compared with the previous method with no adaptive weighting. The proposed method has the potential to be used in clinical applications to reduce registration errors in regions with tumors.

We present a new algorithm for generating tests for single stuck line (SSL) faults in combinational logic circuits using a combination of Boolean and path-oriented techniques. We use Boolean techniques employing the ordered binary decision diagram (BDD) to limit the effect of hard faults on the performance of the algorithm. We use path-oriented techniques similar to those in conventional test generation algorithms to limit the number of algebraic operations that must be performed. The test set generated for each fault is exhaustive in the sense that we find all test patterns which make the fault observable at some primary output. We implemented the algorithm as the program TSUNAMI and applied it to the standard ISCAS '85 and ISCAS '89 benchmark circuits. Results indicate that for circuits which are amenable to analysis by BDD's, TSUNAMI performs significantly better than conventional algorithms such as FAN or EST in generating tests for all targeted faults. Moreover, TSUNAMI finds a large set of test vectors for each fault. The program can easily manipulate these sets of vectors to produce test vectors which test many faults. As a result, we are able to compress the sets of vectors into a very small total number of patterns.

The author addresses static hazards in multi-level combinational logic circuits. A novel approach is introduced based on a uniform hybrid method that is capable of identifying race conditions and detecting all types of hazards: static, logic, function, and dynamic, that have the potential to exist in combinational logic circuits under given conditions. This method is based on a binary switching algebra, and uses hardware simulation techniques together with more formal symbol manipulation mechanisms in order to identify potential hazards in logic design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new method for estimating the glitching contribution to the power dissipation of multilevel combinational logic circuits based on complex-time cellular automata is presented for the first time. To bridge the gap between continuous time, in which the combinational logic circuits operate, and the discrete time, in which cellular automata operate, the concept of complex time is introduced. Both the logic combinational circuit and the cellular automaton model that simulates it, are assumed to exist in a linear complex space, where the real part of the complex time is the continuous time and the imaginary part is the discrete time. Using the complex time concept the proposed model can take full advantage of both the local operation capabilities of cellular and the convenient formulation of VLSI circuit description using two-dimensional matrices and netlists.

According to the goal of independent college to cultivate application service-oriented talents.The paper presents the field programmable gate array(FPGA),Quartus II and Verilog HDL knowledge to the teaching method in the teaching of digital logic circuit using the combinational logic circuits and sequential logic circuits as a design example.The teaching practice shows that this teaching method can motivate students interest in learning.It plays a positive role in promoting students practice ability and innovation consciousness,thus enhance the teaching quality.

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.