A new autosizing algorithm for CMOS combinational logic circuits

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Y}_{{2}}\text{O}_{{3}}$ </tex-math></inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Excellent initial guess functions for simple shooting method in Yb3+-doped fiber lasers

This paper proposes a method for detecting delay faults of gates in a combinational logic circuit. Assuming that a gate of the circuit has a small delay (a unit delay), the generation of a test for the circuit is described. This paper also describes the generation of the timed seven-valued calculus used in the method. The method has been applied successfully to benchmark circuits having unit delay and a fanout weighted delay. The experimental results show that the method has high fault coverage in all the circuits, and that this can be applied to the detection of gross delay faults. The proposed test method is called the ‘SD test’. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(6): 68–76, 1997

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size.

After using side-channel information leaked by the FPGA chip which is embedded with a block cipher algorithm, there is a scheme called improved combinational side-channel attack. This scheme mainly aimed at logical circuits implemented in S-box in background of power consumption attack and we make a level of models by power consumption in combinational logic circuits which is engendered by glitches different from traditional sequential logical circuits which is engendered by flip in the output of register with the Hamming model. In addition, we take advantage of match algorithm in a linear model and in multivariate Gaussian model from template attack to process an important data twice and the key would be recovered. At last, we make a comparison between Hamming model and our model. And prove that this paper improved the attacking efficiency and accuracy and also provided a clue to the security cipher chip from countermeasures.

Objective: To study the specificities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.

The author addresses static hazards in multi-level combinational logic circuits. A novel approach is introduced based on a uniform hybrid method that is capable of identifying race conditions and detecting all types of hazards: static, logic, function, and dynamic, that have the potential to exist in combinational logic circuits under given conditions. This method is based on a binary switching algebra, and uses hardware simulation techniques together with more formal symbol manipulation mechanisms in order to identify potential hazards in logic design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new method for estimating the glitching contribution to the power dissipation of multilevel combinational logic circuits based on complex-time cellular automata is presented for the first time. To bridge the gap between continuous time, in which the combinational logic circuits operate, and the discrete time, in which cellular automata operate, the concept of complex time is introduced. Both the logic combinational circuit and the cellular automaton model that simulates it, are assumed to exist in a linear complex space, where the real part of the complex time is the continuous time and the imaginary part is the discrete time. Using the complex time concept the proposed model can take full advantage of both the local operation capabilities of cellular and the convenient formulation of VLSI circuit description using two-dimensional matrices and netlists.

According to the goal of independent college to cultivate application service-oriented talents.The paper presents the field programmable gate array(FPGA),Quartus II and Verilog HDL knowledge to the teaching method in the teaching of digital logic circuit using the combinational logic circuits and sequential logic circuits as a design example.The teaching practice shows that this teaching method can motivate students interest in learning.It plays a positive role in promoting students practice ability and innovation consciousness,thus enhance the teaching quality.

The functions of the cost curve and transmission losses are existing nonlinear, simultaneous subject to equality and inequality constraints. Mathematically, the solutions of the nonlinear equations of economic dispatch problem may result in multiple solutions, singal solution or no solution. Conventional methods may fail to find all the multiple solutions if the initial guess values are not appropriately located within the convergency region. To overcome this difficulty te homotopy method is suggested for the solution technique. In this paper the homotopy theorem is incorporated with the B-coefficient method to solve the economic dispatch problem. Not only the initial value is easily obtained but also all the multiple solutions can be obtained. So the next exact least cost of economic dispatch can be derived.

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

In this study, high‐throughput and flexible hardware implementations of the CLEFIA lightweight block cipher are presented. A unified processing element is designed and shared for implementing of generalised Feistel network that computes round keys and encryption process in the two separate times. The most complex blocks in the CLEFIA algorithm are substitution boxes ( and ). The S‐box is implemented based on area‐optimised combinational logic circuits. In the proposed S‐box structure, the number of logic gates and critical path delay are reduced by using the simplification of computation terms. The S‐box consists of three steps: a field inversion over and two affine transformations over . The inversion operation is implemented over the composite field instead of inversion over which is an important factor for the reduction of area consumption. In addition, we proposed a flexible structure that can perform various configurations of CLEFIA to support variable key sizes: 128, 192 and 256 bit. Implementation results of the proposed architectures in 180 nm complementary metal–oxide–semiconductor technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared with other related works.

Pareto-domination was adopted to handle not only trade-off between objective and constraints but also trade-off between convergence and diversity on solving a constrained optimisation problem (COP) in this paper like many other researchers. But there are some differences. This paper converts a COP into an equivalent dynamic constrained multi-objective optimisation problem (DCMOP) first, then dynamic version of non-dominated sorting genetic algorithm with decomposition (NSGA/D) is designed to solve the equivalent DCMOP, consequently solve the COP. A key issue for the NSGA/D working effectively is that the environmental change should not destroy the feasibility of the population. With a feasible population, the NSGA/D could solve well the DCMOP just as a MOEA usually can solve well an unconstrained MOP. Experimental results show that the NSGA/D outperforms or performs similarly to other state-of-the-art algorithms referred to in this paper, especially in global search.

This paper presents new algorithms for evaluating the reliability of fault-tolerant combinational logic circuits. In order to model the effects of multiple faults on circuit functionality, we use fault indicators as control variables. We use BDD-based symbolic simulation to avoid the explicit enumeration of faults. We present experimental results on fault-tolerant implementations of several mcnc benchmark circuits. They show that undetectable multiple faults have a large impact on the reliability of fault-tolerant circuits.

The Boolean difference is a well-known mathematical concept which has found significant application in the single fault analysis of combinational logic circuits. One of the primary attributes of the Boolean difference in such situations is its completeness. In this paper we extend the Boolean difference concept to cover multiple fault situations. Expressions are developed which give all possible input patterns that can be applied to combinational logic circuits to demonstrate the presence or absence of a specified multiple fault of the stuck-type class. Such expressions are useful in situations where at most, say, p simultaneous faults need be considered, as well as situations where any multiple fault can exist. In addition the expressions developed are also shown to complete some existing single fault analysis concepts.