A method of parallel-sequential detection of image features in computer vision systems

Computer vision system for automated cell pressure probe operation

TOUCH is a real-time computer vision system that has been developed in order to aid the operation of autonomous underwater vehicles (AUVs) and remotely operated vehicles (ROVs). The algorithm is based on a modified 4-connectivity approach that scans the incoming frames for a target hue range and based upon the largest connected blobs of hue, tracks an object and provides the two dimensional Cartesian coordinates of the desired object. Since few algorithms exist for tracking and recognizing objects in underwater environments, this algorithm provides a way for AUVs and ROVs to acquire, track or recognize objects by using a relatively fast and inexpensive vision system. This paper presents the details on TOUCH, its testing, some areas that warrant improvement and possible course of action for the future.

In this paper, we present an autonomous helicopter with vision based navigation called South China University of Technology unmanned aerial vehicle (SCUAV). A GPS/INS system has been designed and implemented for getting stable navigation information. A Kalman filtering has been used in this system for data fusion. A real-time computer vision system is presented in this paper as the complement of the GPS/INS system. The vision algorithm is designed and implemented in this paper, which is integrated with algorithms for tracking a known landmark and estimating the helicopter positions. A method of image processing is designed for tracking and recognizing known land marks. At the end of the paper, we will present the experiment results to demonstrate our efficacious algorithm.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

The goal of this work is to implement a real-time computer vision system that can run on wearable devices to perform object classification and artwork recognition, to improve the experience of a museum visit through understanding the interests of users. Object classification helps to understand the context of the visit, e.g. differentiating when a visitor is talking with people, or just wandering through the museum, or if he is looking at an exhibit that interests him. Artwork recognition allows to provide automatically information of the observed item or to create a user profile based on what and how long a user has observed artworks.

Programming a Pipelined Image Processor

Continuous real-time monitoring and neural network modeling of apple slices color changes during hot air drying

We present recent results of a performance benchmark of selected low-level vision algorithms implemented on different high-speed embedded platforms. The algorithms were implemented on a digital signal processor (DSP) (Texas Instruments TMS320C6414), a field-programmable gate array (FPGA) (Altera Stratix-I and II families) as well as on a mobile PC processor (Intel Mobile Core 2 Duo T7200). These implementations are evaluated, compared, and discussed in detail. The DSP and the mobile PC implementations, both making heavy use of processor-specific acceleration techniques (intrinsics and resource optimized slicing direct memory access on DSPs or Intel integrated performance primitives Library on mobile PC processors), outperform the FPGA implementations, but at the cost of spending all its resources to these tasks. FPGAs, however, are very well suited to algorithms that benefit from parallel execution.

Real-time computer vision systems that observe the actions of people have received increasing attention as they are important for a broad range of applications. Examples are intelligent man-machine interfaces or intelligent rooms that have the capability to understand the actions of their inhabitants. In this paper we present the design of a stereo vision system for the precise and robust real time tracking of human hands and heads that unlike previous systems uses low-cost industry standard components. The system uses color and motion information to find the human. Using previously calibrated cameras the 3D positions of hands and head are calculated. Because of its client-server architecture the system is scalable to an arbitrary number of cameras and application processes. Experimental results for the performance of the system are given.

This paper describes the teaching and research of signal processing and communications systems that took place during the development of a real-time transceiver and radio channel testbed at Hokkaido University, Japan. Digital signal processing (DSP) concepts were taught and learnt during both the testbed system development and also the results gathering and analysis stages. The performance of a modern multiple antenna communications system is dependent on a number of key parameters, and the student interaction with such a real-time system can assist in the understanding of key but often abstract theoretical concepts. The communications algorithm and architecture overview on a signal processing board containing a Xilinx field programmable gate array (FPGA) and Analog Devices TigerSharc DSP is detailed. The lessons learned and potential uses of the testbed in both teaching and research are also described.

Real-time underwater sorting of edible fish species

Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Cameras for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed processing elements and memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to eighty-one processing elements were implemented and compared to several works from the literature. Using a System-on-Chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.

A new design method for the real-time image processing system based on field programmable gate array (FPGA) and digital signal processing (DSP) structure is presented in the paper. In the practical system, FPGA is used to be logic unit for sensor interface protocol and complete image preprocessing and display of PAL video; DSP is applied as the main processing unit which is extendable for better performance; Modules are connected by user-configurable I/O interface, external memory interface (EMIF) and host-post interface (HPI), which configure the system to be a loosely coupled and cascaded multi-DSP system. Finally, the design approach shows good performance in the real-time image processing system with the capability of real-time processing, extendibility and multi-interface, which is significant for practical application.

3-D Real-time Measurement System of seam outline based on Moiré Projection is proposed and designed. The system is composed of LD, grating, CCD, video A/D, FPGA, DSP and an output interface. The principle and hardware makeup of high-speed and real-time image processing circuit based on a Digital Signal Processor (DSP) and a Field Programmable Gate Array (FPGA) are introduced. Noise generation mechanism in poor welding field conditions is analyzed when Moiré stripes are projected on a welding workpiece surface. Median filter is adopted to smooth the acquired original laser image of seam, and then measurement results of a 3-D outline image of weld groove are provided.

Reconfigurable architectures for parallel execution of image processing tasks