Reconfigurable architectures for parallel execution of image processing tasks

The paper is devoted to the problem of formalization of software-hardware solutions in designing real-time computer vision systems. The main attention is paid to the methods of implementation of low-level operations that find features (simple elements) in the image input to the system. Algorithmic types of detectors of simple elements in images are analyzed from the point of view of hardware organization in computer vision systems. In this connection, the necessary performance and memory resources are estimated. The capabilities of parallel and pipeline execution of detector algorithms are investigated. A method of using a field programmable gate array and a digital signal processor in solving the problem of image processing in real-time computer vision systems is considered in detail.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Programmable logic offers an alternative solution for the computationally-intensive functions found in digital signal processing (DSP). Programmable logic can provide increased DSP system performance at reduced system cost. Programmable logic combines the flexibility of a general purpose DSP plus the speed, density, and low cost of an ASIC implementation. In some applications, programmable logic replaces the DSP processor entirely. In others, programmable logic works in conjunction with the DSP processor, offloading the computationally-intensive function and freeing the processor for other functions. This paper describes an alternative to traditional, general-purpose DSP processors. Programmable logic can implement functions beyond the capabilities of today's DSP processors. Field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs) potentially provide performance increases of an order of magnitude over traditional DSPs with the same flexibility.

Fetal electrocardiogram (ECG) extraction from non-invasive biopotential recordings is a long-standing research topic. Despite the significant number of algorithms presented in the scientific literature, it is difficult to find information about embedded hardware implementations able to provide real-time support for the required features, bridging the gap between theory and practice. This article presents the NInFEA (non-invasive fetal ECG analysis) tool, an embedded hardware/software framework based on the hybrid dual-core OMAP-L137 low-power processor for the real-time evaluation of fetal ECG extraction algorithms. The hybrid platform, including a digital signal processor (DSP) and a general-purpose processor (GPP), allows achieving the best performance compared with single-core architectures. The GPP provides a portable graphical user interface, whereas the DSP is extensively used for advanced signal processing tasks. As a case study, three state-of-the-art fetal ECG extraction algorithms have been ported onto NInFEA, along with some support routines needed to provide the additional information required by the clinicians and supported by the user interface. NInFEA can be regarded both as a reference design for similar applications and as a common embedded low-power testbed for real-time fetal ECG extraction algorithms.

This thesis aims to develop an embedded image processing board, which can be used to realize various image feature extraction and processing algorithms for robotic applications. The circuitry of this image board can be divided into two parts, one is for a digital signal processor (DSP) and the other for a field programmable gate array (FPGA). A low power, small size CMOS image sensor with YUV4:2:2 image format and 512x480 pixel size is adopted for image acquisition. The DSP module is mainly used for implementing image processing algorithms, while the FPGA module for lower level image processing and sensor control functions. In this work, the TMS320C6414TGLZ7 DSP from Texas Instruments Corporation and the EP2C35F672C6 FPGA from Altera Corporation were selected for the image board. In this work, speeded-up robust features (SURF) algorithm has been successfully realized on the developed image board. An USB interface with average throughput of 22MB/sec works to transfer acquired image frames and extracted SURF descriptors to a personal computer, where feature matching is executed. Experimental results show that the refresh period of frame grabbing is about 33.5ms. When the number of SURF descriptor is equal to 64, the computing time is about 417.5ms; when the number of SURF descriptor is equal to 199, the computing time is about 985ms. The typical matching rate varies from 70.2% to 20%, depending on the threshold of the patterns used in feature extraction.

This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP board, a video board and a host workstation. The IMAP board consists of eight highly-integrated IMAP LSIs and a dedicated control LSI (RVSC). The IMAP chip integrates 2 Mb image memory and 64 processing elements that operate in the SIMD mode. The RVSC chip performs global data operations efficiently without interactions with the host workstation, as well providing an instruction stream to the IMAP chips. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing tasks are carried out within about 0.1-0.7 ms, which is about 50-300 times faster than the video frame rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Describes a parallel-processor LSI chip (the Integrated Memory Array Processor, IMAP) and a compact real-time vision system (RVS-2). The IMAP integrates 64 8-bit processors, which operate in a SIMD manner, and 2-Mbit image memory on a single chip, and has peak performance of 3.84 GIPS. The RVS-2 consists of 8 IMAPs, a video interface, a control LSI chip (the Real-time Vision System Controller, RVSC) and a host workstation. RVSC is a 16-bit processor which carries out global data operations as well as providing an instruction stream to IMAP processors. In the RVS-2 system, the IMAP processors accomplish data-parallel operations, the RVSC applies global data operations to the results, and the host workstation carries out higher-level recognition tasks using the results obtained by the IMAPs and the RVSC. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing is carried out in 0.1 to 0.7 ms, which is 50 to 300 times faster the video rate.

The digital image acquisition and processing technology already mature also in domains and so on visual communication obtains day by day[1]. However, the image acquisition and processing technology had many kinds, for example white balance processing and image denoising methods. The traditional image acquisition and processing systems are implemented using software by the PC or DSP chip[2], and sometimes software in series can not meet the requirement of high speed image processing. this article has given FPGA in the image acquisition and processing simple application, applied FPGA in the image acquisition and processing to be possible to enhance the image processing the speed, reduced takes the logical unit. The system designed by above-mentioned way achieves a satisfying effect by experimental verification.

The 2022 International Conference on Image Processing and Intelligent Information Systems (IPIIS 2022) was successfully held online during October 22-23, 2022 in Zhengzhou, China. In the context of the conference, scholars and experts in the fields of image processing and intelligent information systems, involved both in experimental and theoretical research, were invited from various universities and institutions. The conference focused on the most recent advancements in topics such as 'Wireless Sensor Networks', 'Digital Signal Processing', 'Embedded Systems' and others.&#x0D; The main goal of IPIIS 2022 was to present the related research work, to promote the cooperation of experts and scholars in these fields, to share the research achievements both on a national and international level. This collection of proceedings compiles oral and paper presentations submitted by the authors and scrutinized by the editorial committee.&#x0D; Because of restrictions on travel and indoor activities related to COVID-19, we were forced to hold the conference online only. Attendees were notified well in advance that the on-site conference was changed to an online conference, where the timeline and order of the talks were defined. The video conference was held on the original set dates. Due to the large variety of topics and the relatively large number of attendees, the conference was separated into main and parallel sessions. Each plenary speaker gave an oral presentation of 30-40 minutes accompanied by his slides' material, allocated for questions and discussion.&#x0D; The organizing and editorial committees of IPIIS 2022 hope you can enjoy the reading of this volume. Additionally, we want to thank all authors and participants for providing their valuable contributions for these proceedings, as well as the reviewers for their constructive recommendations and feedback aiding to improve the presented articles.&#x0D; IPIIS Organizing Committee&#x0D; Zhengzhou, China

Programming a Pipelined Image Processor

Implementation of a real-time image visualization system on a reconfigurable chip (FPGA) is proposed. The system utilizes an innovative stereoscopic image capture, processing and visualization technique. Implementation is done as a two stage process. In the first stage, the stereo pair is captured using two image sensors. The captured images are then synchronized and sent to the second stage for fusion. A controller module is developed, designed, and placed on the FPGA for this purpose. The second stage is used for reconstruction and visualization of the 3D image. An innovative technique employing dual-processor architecture on the same single FPGA is developed for this purpose. The whole system is placed on a single PCB resulting in a fast processing time and the ability to view 3D video in real-time. The system is simulated, implemented, and tested on real images. Results show that this system is a low cost solution for efficient 3D video visualization using a single chip.

A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data streams (SIMD) and reconfigurable architecture. Equipped with eight SIMD-controlled 16-bit datapaths which can also be reconfigured as two 32-bit datapaths, the DSP core can process both 16-bit and 32-bit data in parallel, showing high performance, especially in the applications preferring parallel data flow computations, such as image processing. The SIMD scheme is extended with the instant-scalability of datapaths (ISSIMD), which offers the DSP a capability of dimension-controllable vector processing, so that to provide flexibility for different embedded applications. A first prototype in 0.18-/spl mu/m CMOS technology has been fabricated, which achieves IGMACS performance at the clock of 125 MHz.

In this paper, a new architecture is proposed for high-speed Digital Down Conversion (DDC) for communication signal processing. The proposed architecture integrates conventional Polyphase Filter with Polyphase Mixer (PFPM) for decimation in DDC. The PFPM architecture decreases both the rate of the mixer and filter and can process the signals with a very high sample rate, which cannot be realistically implement in conventional DDC in a General Purpose Processor (GPP) such as Field Programmable Gate Array (FPGA) or Digital Signal Processor (DSP). Simulation and experiment have been done to verify the availability of the PFPM architecture. These results show that the proposed PFPM architecture reduces the operation rate of the mixer and well agrees with the conventional DDC architecture.

Continuous advances in silicon technology enable the development of complex system-on-chip as cooperation among digital signal processors (DPSs), general purpose processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC) - statically and in a fast manner - and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected hardware-software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper.

There are different factors that one would like to optimize when designing a VLSI circuit. Often they cannot be optimized simultaneously, only improve one factor at the expense of one or more others. The design of an efficient integrated circuit in terms of Power, Area and Speed has become a very challenging problem. Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronic products with more backup and less weight. Adders and multipliers are the most important arithmetic units in a general purpose processors and the major source of power dissipation. The objective of a good multiplier is to provide a physically compact, high speed and low power consuming chip. Fast multipliers are the key components of many high performance systems such as FIR filters, Microprocessors, Digital signal processors etc. A system performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is the major design issue. However, area and speed are usually conflicting constraints so that improving speed results in larger areas. In this paper we are using the Modified Carry Save adder which is used to speed up the final addition in many parallel multipliers.KeywordsFast MultiplierHigh Speed AdderPower-Delay ProductField Programmable Gate ArrayParallel Multiplier