An Area Efficient and Low Power Multiplier Using Modified Carry Save Adder for Parallel Multipliers

Multiplier is one of the major hardware circuits of microprocessor and high performance systems such as digital signal processor; FIR filters, processing operations like Convolution, Cross Correlation, and auto-correlation of discrete signals, digital Image processing applications such as edge detection etc. The major design constraint of multiplier is speed which is affected due to propagation delay of adders, low power consumption, area which is conflicting constraints of speed etc. Our designs propose tradeoffs among computational time, latency and throughput of Vedic digital multiplier. This paper presents the high speed and low power multiplier logic design using Vedic multiplication method. The simulations have been carried out in Xilinx simulator for timing waveform simulation and a CMOS layout of Vedic multiplication is implemented in microwind layout simulator tool for analysis of power dissipation using 50nm technology.

In the VLSI circuits, power dissipation is a critical design parameter and it plays a vital role in the performance of different digital systems. The decrease in chip size along with the increase in chip density and complexity will increase the difficulty in designing higher performance and low power digital systems. Therefore, achieving a fast and low power system is the major concern of VLSI designers. Most of the digital systems have different math operations in their architectures. This paper focuses on the multiplication operation. Multiplication requires more iterations, long time, large area, and consumes high power of the digital system compared with the other basic computation operations. Hence to improve the system's performance, it is required to design a high speed and low power multiplier. In this paper, a dynamic power dissipation is targeted; therefore, different designs of multiplier algorithms such as a sequential multiplier, array multiplier, Booth’s multiplier (Radix-2), and modified Booth’s multiplier (Radix-4) are proposed to investigate the design that consumes the lowest dynamic power. New techniques such as VHDL and Basic Logic Elements are presented and applied to the proposed designs. The VHDL approach satisfies the highest optimization criteria in dynamic power at 87% for the sequential multiplier than the traditional ones.

Multipliers are important hardware components in most digital and high-speed systems, such as microprocessors, digital signal processors, and FIR filters. In reality, Multipliers, which are complicated units, are responsible for the total speed, size, and power consumption of digital systems. Multiplication in digital systems has a wide range of requirements for speed, size, power consumption, and other parameters. It comprises of partial product production, partial product reduction, and lastly carry-propagate addition. The Multiplier design focuses on minimizing power dissipation while still maintaining other parameters. To obtain considerable power savings in VLSI design, the dynamic power dissipation of multipliers must be reduced. The fundamental goal of this effort is to choose an appropriate adder that consumes less power, runs at a high speed, and is plainly less expensive. The available 8-bit adders, such as the Carry Select Adder, Ripple Carry Adder, Carry Look Ahead Adder, and Kogge Stone Adder, are investigated. Among the adders tested, the Kogge Stone Adder performs the best. This adder may be used to create efficient multipliers.

As Field programmable Gate Array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPCA technology. As this paper demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 5 MHz (with a clock rate of at least 40 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation. Distributed arithmetic was determined to be the most optimal structure for a FPGA FIR design, although future research may show that fast FIR algorithms or filtering in the frequency domain might give better results.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

In this paper we have designed a novel dedicated low power 64 bit digital comparator. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. A Low Power 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on power delay product. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the circuit. Simulation of the proposed design is performed at 180 nm technology in Tanner EDA Tool.

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Low power design of VLSI c ircuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP).Multiplier has an important role in the DSPs.Without degrading the performance of the processor, low power parallel mult ipliers are needed to be design.Bypassing is the widely used technique in the DSPs when the input operand of the mult iplier is zero.A Row based Bypassing Multiplier with comp ressor at the final addition of the ripple carry adder (RCA) is designed to focus on low power and high speed.The proposed bypassing mu ltip lier with co mpressor shows high performance and energy efficiency than Kuo mu ltiplier with Carry Save Adder (CSA) at the final RCA.

This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power design of Vedic Multiplier. Temperature plays an important role on the performance of any device. The primary purpose of this research is to enhance the thermal stability of the wireless communications. Energy efficient IO standards are used to decrease the power dissipation of Vedic Multiplier and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy efficient Vedic Multiplier on various FPGA using LVCMOS and HSTL I/O standard. LVCMOS is an acronym for Low Voltage Complementary Metal Oxide Semiconductor and HSTL is an acronym for High Speed Transceiver Logic. In this Vedic Multiplier, we are using three LVCMOS I/O standard and nine HSTL I/O standard. In order to test the thermal sustainability of our Vedic Multiplier design, we are testing it in three different room temperatures i.e. 20, 30, and 40 °C. Using LVCMOS25, there is 12.99, 19.23 and 10.28% reduction in power dissipation on 90, 65 and 40 nm FPGAs respectively. For LVCMOS25, when our Vedic Multiplier design is migrated from 40 nm design to 90 nm FPGA design, there is 87.72% reduction in power dissipation of Vedic Multiplier when temperature is kept constant at 20 °C. When temperature is scaled down from 50 to 20 °C there is 12.45, 14.93, 12.84, 9.45 and 8.48% saving in power dissipation on using HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI and HSTL_I_DCI_18 IO Standard respectively on 90 nm FPGA.

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, micro processors and digital signal processors etc. A system's performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system and also it is occupying more area consuming. The Carry Select Adder (CSLA) provides a good compromise between cost and performance in carry propagation adder design. A Square Root Carry Select Adder using RCA is introduced but it offers some speed penalty. However, conventional CSLA is still area-consuming due to the dual ripple carry adder structure. In the proposed work, generally in Wallace multiplier the partial products are reduced as soon as possible and the final carry propagation path carry select adder is used. In this paper, modification is done at gate level to reduce area and power consumption. The Modified Square Root Carry Select-Adder (MCSLA) is designed using Common Boolean Logic and then compared with regular CSLA respective architectures, and this MCSLA is implemented in Wallace Tree Multiplier. This work gives the reduced area compared to normal Wallace tree multiplier. Finally an area efficient Wallace tree multiplier is designed using common Boolean logic based square root carry select adder.

This paper presents the modification of existing prominent multipliers like Wallace multiplier and Truncated Multiplier in order to improvise them in terms of power and area. In the existing Wallace multiplier architecture, the Carry Save Adder is replaced with Modified Carry Save Adder (MCSA)and further the full adder in the MCSA is implemented using Multiplexer. Similarly the regular full adder in the Truncated multiplier has been replaced with mux based full adder to achieve low area and power. Simulation of 8 × 8 Multiplier has been carried out with Modelsim 6.3c and Synthesis is carried out by Xilinx10.1. Results obtained show that the proposed modified multipliers offer low power and reduced area than the existing Multipliers.

Floating-point arithmetic has various applications in the field of Science and Engineering. Specially, need of high precision floating-point multipliers is observed in Digital Signal Processing- like in filtering and transformations . High speed signal processing demands for high speed hardware. Though, various high level languages based implementations of floating-point multiplier are observed so far, but the hardware based implementation has still remained a bottleneck. With the development of Very Large Scale Integration (VLSI) technology, Field Programmable Gate Array (FPGA) has become the best candidate for implementing floating-point multipliers (due to their high integration density, low price, high performance and flexible applications). In this work, we have shown the implementation of IEEE-754 single precision floating-point multiplier on FPGA using carry-look ahead adder (for exponent addition). The multiplier may be used in adaptive filters for multiplying the fractional step size (mue) to update the filter weights. This paper also presents the comparative analysis of proposed design with Spartan 6 FPGA's built-in IPcore for floating-point multiplier. The results are compared in terms of recourse utilization, power consumption, observed delay, logic levels and maximum achieved frequency. It is shown that our design is better in terms of achieved frequency with a small increase in resource utilization.

In this paper, two-dimensional Discrete Wavelet Transform (2-D DWT) based image compression is presented with the help of developed Enhanced square root carry select adder (ESCSLA). The Enhanced Carry select adder is replacing the RCA and BEC unit to D-latch circuit. It provides better results than compared to the conventional adders. DWT and ESCSLA circuit is designed through Very Large Scale Integration (VLSI) System design environment. Low power consumption, less area and high speed are the main concerns in VLSI System design. Hence, our aim is to reduce the hardware complexity of ESCSLA and improve the performance of DWT in terms VLSI concerns. In our work, three levels of decomposition are made for image compression. With the help of pixel values of image and Enhanced square root carry select adder circuit, 2-D DWT image compression technique is implemented through Verilog HDL design. The performance of ESCSLA circuit is better than conventional Binary to Excess1 (BEC) based Square Root Carry Select Adder (SQRT CSLA) in terms of silicon area and power consumption. Hence, the performance of DWT also increased when incorporating EHRCA circuit into addition process of DWT computation.

Parallel FIR filter is the need of many low power and high speed DSP applications. In this paper, fast FIR algorithm based parallel symmetric FIR filter using Han-Carlson adder based vedic multiplier is proposed. FFA algorithm reduces the multiplier count as compared to the traditional parallel design. In order to improve the performance of the proposed filter, recently developed Han-Carlson adder based Vedic multiplier is used. In the proposed design the adder unit is also implemented using Han-Carlson adder. In the proposed design two and three parallel FIR filters of order 24 and 72 are implemented using VHDL. The implementation results show that the proposed architecture provides low critical path delay and power dissipation as compared to the conventional one. With the advantage of low delay and power, proposed architecture is useful in modern signal processing and communication applications.