A Comparative Performance Analysis of Low Power Bypassing Array Multipliers

For the efficient filter implementation reconfigurability and low power have always been the main concerns. This paper introduces two new low power and high speed reconfigurable parametric equalizer designs. These designs are based on the row bypassing multipliers which are implemented using carry save adder (CSA) and ripple carry adder (RCA). The primary power reduction is procured by turning off adders when the multiplier operands are zero. In addition, the proposed equalizers are implemented with parallel architecture of multipliers to shorten the delay time. The proposed designs can be dynamically reconfigured with erratic coefficients that are only constrained by their order and coefficient world length. These parametric equalizers have been implemented and tested on Vertex-IV field programmable gate array (FPGA) board. The efficacy of the proposed design method is presented with an example. The performance of both the designs is evaluated and compared in terms of area (number of slices), speed, i.e., maximum frequency and power consumption. The results depict that the CSA row bypassing multiplier based parametric equalizer achieves 11% speed enhancement and 18% area reduction in comparison with RCA row bypassing multiplier based parametric equalizer. While the power dissipation of the later equalizer is 5% less than the former one.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

Adders play a central role in arithmetic computations as well as digital signal processing. Besides addition, adders are used in multiple operations in processors. Based on our requirements upon variegated parameters our choice on adders can also be changed. Most digital systems, such as processors or computers, have 32-bit architecture, which includes 32-bit integers, registers, and memory locations, among other things. As a result, optimising 32-bit adders minimises total latency and thus enhances speed. In this work, performance analysis of 32-bit adders is compared by the Verilog programming language. 32-bit adder design is highly crucial as its architecture is widespread and used widely, and it is so hard to design. Designing several adders of 32 bit such as carry save adder (CSA), carry look ahead adder (CLA), ripple carry adder (RCA), modified carry select adder (MCSA), carry skip adder (CSKA), kogge stone adder (KSA) and carry select adder (CSLA), are explained in this work based on memory usage and delay. Discussions on adder types are made that aids in reducing the time usage on tedious tasks. CLA and CSKA were compared. Synthesis and simulation are done using Xilinx ISE tool. The simulation results help in the determination of the attributes that were assorted.

The Reversible logic gates implement the functions which are having one to one mapping between the input and output. Unlike irreversible logic circuits the information cannot be lost as the input vector can be recovered from the corresponding output vector. The dissipation of heat is also less in reversible logic gates. Therefore the reversible logic gates have immense number of applications in Low power CMOS design, quantum computing, Nano technology and digital signal processing. This paper proposes a novel 4×4 bit reversible fault tolerant MAC unit. The MAC unit Composed of a multiplier, adder and an accumulation unit. The Ripple Carry Adder and multiplier used in the proposed work were designed using parity preserving gates. The basic building blocks for adder and multiplier used were IG gate, Fredkin gate which are parity preserving gates. Therefore the proposed MAC unit has characteristic attribute of detecting any errors in output side. The synthesis and simulation was done by using Xilinx software and Model Sim Simulator.

Multipliers are important hardware components in most digital and high-speed systems, such as microprocessors, digital signal processors, and FIR filters. In reality, Multipliers, which are complicated units, are responsible for the total speed, size, and power consumption of digital systems. Multiplication in digital systems has a wide range of requirements for speed, size, power consumption, and other parameters. It comprises of partial product production, partial product reduction, and lastly carry-propagate addition. The Multiplier design focuses on minimizing power dissipation while still maintaining other parameters. To obtain considerable power savings in VLSI design, the dynamic power dissipation of multipliers must be reduced. The fundamental goal of this effort is to choose an appropriate adder that consumes less power, runs at a high speed, and is plainly less expensive. The available 8-bit adders, such as the Carry Select Adder, Ripple Carry Adder, Carry Look Ahead Adder, and Kogge Stone Adder, are investigated. Among the adders tested, the Kogge Stone Adder performs the best. This adder may be used to create efficient multipliers.

High-speed multiplication is a fundamental requirement in modern computing systems, including applications in digital signal processing (DSP), artificial intelligence (AI), and cryptography. This paper presents an optimized 64-bit Dadda multiplier incorporating a Brent-Kung Adder (BKA) and 4:2 compressors to enhance speed and efficiency. The Dadda multiplier is widely recognized for its reduced number of reduction stages, significantly minimizing delay and hardware complexity. The integration of the Brent-Kung Adder, a parallel prefix adder with logarithmic delay, further improves performance by reducing carry propagation delay in the final addition stage. The proposed design is implemented in Verilog and synthesized on an FPGA to evaluate its efficiency in terms of delay, power consumption, and area utilization. A comparative analysis is conducted against 32-bit Dadda multipliers utilizing Ripple Carry Adder (RCA) and Carry Select Adder (CSLA), demonstrating that the 64-bit Dadda multiplier with BKA achieves superior speed while maintaining reasonable power and area efficiency. Simulation results reveal that the proposed design achieves a propagation delay of 28.228 ns, significantly lower than traditional approaches. The inclusion of 4:2 compressors further optimizes partial product reduction, ensuring a more efficient multiplication process. By leveraging an optimized reduction strategy and an efficient parallel prefix adder, this work provides a robust solution for real-time applications requiring high-speed arithmetic computations. The balance between speed, power, and hardware utilization makes this design a practical choice for applications demanding efficient multiplication operations.

Adders are digital circuits that perform addition operation. There are various types of adder structures such as Ripple carry adder (RCA), carry look ahead adder (CLA) , carry select adder (CSLA) , carry save adder(CSA), carry skip adder, carry increment adder and so on. Again CSLA is of two types that is linear carry select adder (LCSLA) & square root carry select adder (SQRT CSLA). To design an efficient adder circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In this paper performance analysis of different adder structures like RCA, CLA, LCSLA and SQRT CSLA has been carried out and then a Heterogeneous adder structure is proposed, which compose of four different sub homogeneous adders (RCA, CLA, LCSLA and SQRT CSLA). The heterogeneous adder structure is used to demonstrate the tradeoffs between the speed and area. In this paper, all adder structures i.e., RCA, CLA, LCSLA and SQRT CSLA are to be designed and are to be compared with each other in terms of delay and area. Then by using the homogeneous adder structures different heterogeneous adder structures of 16-bit size are to be designed. Different heterogeneous adder architectures are compared with each other in terms of delay (ns) and area (number of LUTs). All the adder structures are designed using VHDL with the help of ISE Xilinx design suite 14.2 and functionally simulated using ISIM simulator. All the designs are to be synthesized using Xilinx XST synthesizer.

Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital filters etc. Multiplier is designed, considering the tradeoffs between low power and high speed. The bypassing multiplier is an improvement, over Braun multiplier which is one of the parallel array multiplier. The tradeoffs i.e. dynamic power and delay of the Bypassing multipliers can be reduced by using different adders. This paper presents a comparative study of 1-dimensional and 2-dimensional bypassing multipliers using different adders on basis of delay, area and power and for 4x4, 8x8 and 16x16 bits in FPGA Spartan – 3E using Xilinx 12.4 ISE and Synopsys respectively.

The design of Multiplier-Accumulator (MAC) unit can be implemented by using the Vedic multiplier along with the reversible logic gates. The designing of Vedic multiplier is designed by using the new sutra called “Urdhava Triyagbhayam”. The performance of the MAC operation depends on the multiplier unit and the adder units. Here the designing of a multiplier and an adder can be designed by using the reversible gates to get the high speed of operation and also a Vedic multiplier is used for the higher performance, lesser area and to reduce the partial products. Nowadays reversible computing will take a more preferable for low power dissipation, higher speed of operation. Here, we proposed an 8, 16, 32, 64-bit Vedic multiplier is designed by using the carry save adder(CSA), the kogge stone adder(KSA) and the DKG adder out of these the proposed DKG gate adder is having the high speed of operation. The comparative analysis is carried out among the ripple carry adder (RCA), carry save adder, kogge stone adder. Finally, it has been proved that the proposed DKG gate with Vedic multiplier-adder is having the high speed of operation. The overall Simulation and synthesis process is carried out with Xilinx ISE 14.7 and is dumped on the FPGA Zynq board.

Multipliers play an extremely important role when we are concerned with arithmetic operations and digital signal processing. Therefore, the execution time for these multipliers should be high in order to speed up the calculation and get faster results. Hence, designing a multiplier suiting all the possible parameters such as processing speed, the fabrication area and also the power consumption is important. In multipliers, adders play a very crucial role as they are the basic building blocks for any arithmetic operations. Thus array multipliers having varied adder architectures like carrying ripple adder (RCA), carry look ahead (CLA), and few configurations of carry save adder (CSA) like CSA, conventional CSA with half adder, CSA with the last stage RCA and CSA with the last stage CLA were designed and analysed for performance parameters like maximum combinational path delay, total power consumption and area utilisation using Xilinx ISE platform. The designed multipliers were targeted for Spartan 6 XC6SLX9 CSG324 speed-2 with 16 MB flash space, 100MHz oscillator, 8 LEDs and 4 switches for user-defined purposes.

There are different factors that one would like to optimize when designing a VLSI circuit. Often they cannot be optimized simultaneously, only improve one factor at the expense of one or more others. The design of an efficient integrated circuit in terms of Power, Area and Speed has become a very challenging problem. Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronic products with more backup and less weight. Adders and multipliers are the most important arithmetic units in a general purpose processors and the major source of power dissipation. The objective of a good multiplier is to provide a physically compact, high speed and low power consuming chip. Fast multipliers are the key components of many high performance systems such as FIR filters, Microprocessors, Digital signal processors etc. A system performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is the major design issue. However, area and speed are usually conflicting constraints so that improving speed results in larger areas. In this paper we are using the Modified Carry Save adder which is used to speed up the final addition in many parallel multipliers.KeywordsFast MultiplierHigh Speed AdderPower-Delay ProductField Programmable Gate ArrayParallel Multiplier

We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

Finite Impulse Response (FIR) filters, microprocessors and digital signal processors are the core system of multipliers. The Multiplier and Accumulator Unit (MAC) is the predominant block in a Digital Signal Processing (DSP) system. The objective of MAC is implementation of signal processing with high performance but multiplier most of the time occupies much area and become power consuming circuits. In this paper, a Modified Russian Peasant Multiplier (MRPM) using Hancarlson adder (HA) has been proposed. According to Russian Rules, a Divide and conquer technique is used in the multiplication process. But, in the perspective of digital design, only shifters and adders are used in the Russian Peasant Multiplier (RPM) to produce a Partial Product Generation (PPG). In this paper, we present an approach towards the reduction of delay in existing RPM by using HA, in the partial product reduction stage and proposed RPM with HA at Partial Product Addition (PPA). The proposed design is also compared to the RPM with Ripple Carry Adder (RCA), Carry Selector Adder (CSA) and 8-2 Adder Compressors (AC) in terms of propagation delay. The proposed design enhances speed of the system by 80.4% compared to the RPM using RCA, 81.7% compared to RPM using CSA and 77.5% compare to RPM with 8:2 adder compressors (AC’s). The total operation is coded with Verilog Hardware Description language (HDL) using Model-Sim 6.3C, synthesized by using the Xilinx Integrated Software Environment (ISE) 14.7 design tool.

Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.