Design and performance analysis of array multiplier (using Xilinx)

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

Addition is an indispensable operation for any high speed digital system, digital signal processing or control system. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. In this work technology independent logic optimization is used to design 1-bit full adder with 20 different Boolean expressions and its performance is analyzed in terms of transistor count, delay and power dissipation using Tanner EDA with TSMC MOSIS 250nm technology. All the Boolean expressions are realized in terms of CMOS logic. From the analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.

In digital systems design, the high-speed adders play an imperative role in modules like adders, multipliers, division, etc. to obtain the results quickly. In digital signal processor and computer data path circuits, carry look-ahead adder (CLA), carry save adder (CSA), carry select adder (CSeA) and carry skip adder are the mostly used fast adders to improve the performance of a system. This work mainly emphasizes on fault-tolerant carry save adder using hardware redundancy configurations for the betterment of reliability at the cost of area. The popular methods like dual (DMR) and triple modular redundancy (TMR) are implemented to detect only but not correct an error and tolerate single event upset (SEU) error respectively. To tolerate multiple errors, for example, two, three and four errors, the 5-modular (quintuple), 7-modular (septuple), and 9-modular (nonuple) redundancy configurations are used respectively. For experimental results, the implementation of a simple addition of four 4-bit numbers is considered on Altera FPGA EP4CE115F29C7 device using Quartus II synthesis software tool. Simulation results reveal that for example in nonuple MR, CSA using CSeA final stage obtain higher performance (45.7 MHz) with moderate power dissipation as 173.36 mW and at the cost of more LEs (216).

In the province of wireless receivers, biomedical equipment, and portable/mobile devices, the demand for Very Large Scale Integration (VLSI) systems that optimize space, minimize power consumption, and deliver high performance is dominant. At the core of these systems, adders play a pivotal role as the primary component of arithmetic units. This paper proposes a ripple carry propagate adder with a high-speed area-efficient. The two’s complement representation is employed for adding two numbers, a common practice in various systems dealing with n-bit input sequences. Microprocessors and digital signal processing use these carry adders. The carry output of every finished adder stage is useful as a carry input to the one behind it. This procedure is continued until the last complete adder stage is reached. Each carry output bit in an entire adder is therefore rippled to the next stage. An exact (forward) carry adder be linked with the proposed structure to generate hybrid adders with tunable accuracy levels. The practical implementation of proposed model is carried out using Xilinx ISE Design Suite 13.4, showcasing its feasibility for real-world applications.

Low power design of VLSI c ircuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP).Multiplier has an important role in the DSPs.Without degrading the performance of the processor, low power parallel mult ipliers are needed to be design.Bypassing is the widely used technique in the DSPs when the input operand of the mult iplier is zero.A Row based Bypassing Multiplier with comp ressor at the final addition of the ripple carry adder (RCA) is designed to focus on low power and high speed.The proposed bypassing mu ltip lier with co mpressor shows high performance and energy efficiency than Kuo mu ltiplier with Carry Save Adder (CSA) at the final RCA.

Fast and efficient multiplication is also a pillar of contemporary digital signal processing (DSP) and cryptography as well as edge computing architectures. Traditional Wallace Tree multipliers provide greater speed with parallel reduction, but in many applications have high area and power overhead, thus they are typically not applicable in low-power SoC and IoT applications. To address these issues, an optimized pipelined Wallace Tree multiplier is designed that has a small two-stage carry-save adder (CSA) pipeline, a single 8-bit carry-lookahead adder (CLA), and power-conscious register activation using stage-enable signals. The proposed architecture, synthesized with Cadence Genus with slow process conditions, is 75 percent smaller (reducing 7224.94 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to 1814.29 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>), 80 percent less power (down to 168 μW) and has a 26 percent shorter critical path delay (down to 256 ps) than the conventional design. These findings show a balanced multiplier architecture that is optimized in terms of speed, area and power consumption, which is most appropriate in low-power ASIC and FPGA accelerators in next-generation IoT and edge-AI systems.

We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper gives a newfangled dimension to superconducting logic which is the successor of CMOS logic and other superconducting quantum logic. Reciprocal Quantum logic (RQL) is proposed to achieve the less memory capability. RQL is a modified version of Rapid Single Flux Quantum (RSFQ). We designed and analyzed different RQL logic like half adder, full adder, counter, and Carry Save Adder (CSA) and we achieved an increase in clock speed compared to RSFQ logic by 20%. The designs are made of AndOr and AnotB gate operation and analyzed using WRSPICE software.

For the efficient filter implementation reconfigurability and low power have always been the main concerns. This paper introduces two new low power and high speed reconfigurable parametric equalizer designs. These designs are based on the row bypassing multipliers which are implemented using carry save adder (CSA) and ripple carry adder (RCA). The primary power reduction is procured by turning off adders when the multiplier operands are zero. In addition, the proposed equalizers are implemented with parallel architecture of multipliers to shorten the delay time. The proposed designs can be dynamically reconfigured with erratic coefficients that are only constrained by their order and coefficient world length. These parametric equalizers have been implemented and tested on Vertex-IV field programmable gate array (FPGA) board. The efficacy of the proposed design method is presented with an example. The performance of both the designs is evaluated and compared in terms of area (number of slices), speed, i.e., maximum frequency and power consumption. The results depict that the CSA row bypassing multiplier based parametric equalizer achieves 11% speed enhancement and 18% area reduction in comparison with RCA row bypassing multiplier based parametric equalizer. While the power dissipation of the later equalizer is 5% less than the former one.

Multiplication is one of the most basic processes, in digital signal processing applications. To process the instructions, most processors require multiplication. Because multipliers are employed in almost all arithmetic operations, they consume the majority of time and power. As a nutshell, the multiplier's efficiency is critical in terms of enhancing processor performance. The array multiplier is one of the most efficient multipliers since it is both quick and simple. However, power consumption is high. The basic components of an array multiplier are adders. The multiplier's efficiency will improve if the adders are much more efficient. The prior study used Complementary Metal Oxide Semiconductor (CMOS) to construct a Quaternary Carry-Lookahead Adder (CLA) that substitutes the adder circuit in the array multiplier. Quaternary number system circuits are quicker than binary number system circuits and can execute arithmetic operations without carry. However, Quaternary circuits take up more space. As a solution, the Quaternary Carry Increment Adder (CIA) is proposed. The proposed adder consumes less power and occupies less area than the existing Quaternary CLA. In the array multiplier, the Quaternary CIA substitutes the Quaternary CLA. This helps to lower the multiplier's power and area consumption. Tanner EDA tool is used to designing the circuits and were simulated with 180 nm technology. Various parameters such as delay, power and power-delay product of the existing and the proposed are measured and compared.

Recent researches are mostly focused on technology scaling as well as device size minimization design techniques following Moore’s law. Conventional computing architectures are unable to fulfill modern application demands. Memristor is a promising alternative device which has been developed by many researchers [2] to draw attention of its structure for numerous applications which includes computational logic, memory implementations and neuromorphic systems. This paper emphasizes the basic properties of memristor at the device level. Different digital circuits have been designed for logic operations and DSP applications. Design methodologies are developed for proper circuit design, and circuit parameters are taken from a very detailed device model and optimization techniques. The transient response of Hybrid CMOS-memristor based logic gates and different adder circuits (i.e, half adder, full adder, carry-save adder) and multiplier circuit are performed in Cadence 180nm technology.

Adders play a central role in arithmetic computations as well as digital signal processing. Besides addition, adders are used in multiple operations in processors. Based on our requirements upon variegated parameters our choice on adders can also be changed. Most digital systems, such as processors or computers, have 32-bit architecture, which includes 32-bit integers, registers, and memory locations, among other things. As a result, optimising 32-bit adders minimises total latency and thus enhances speed. In this work, performance analysis of 32-bit adders is compared by the Verilog programming language. 32-bit adder design is highly crucial as its architecture is widespread and used widely, and it is so hard to design. Designing several adders of 32 bit such as carry save adder (CSA), carry look ahead adder (CLA), ripple carry adder (RCA), modified carry select adder (MCSA), carry skip adder (CSKA), kogge stone adder (KSA) and carry select adder (CSLA), are explained in this work based on memory usage and delay. Discussions on adder types are made that aids in reducing the time usage on tedious tasks. CLA and CSKA were compared. Synthesis and simulation are done using Xilinx ISE tool. The simulation results help in the determination of the attributes that were assorted.

Rivest, Shamir, Adleman (RSA) algorithm can be used in cryptography to send confidential messages in secure manner. RSA cryptosystem is based on modular multiplication to factorize the large integers. Montgomery modular multiplication can be used as modular multiplication because it is one of the efficient and fastest modular multiplication. Montgomery algorithm is based on add and shift operation, so Carry save adder (CSA) can be used in order to overcome the carry propagation at each addition. In this Montgomery multiplier, the CSA choses the operands and converts the addition result from carry save format to binary form. Accordingly, the architecture can use less hardware and give short critical path delay to do one modular multiplication. In this paper, the Montgomery modular multiplication uses a modified or configurable Carry save adder (CCSA). The CCSA is designed with one full adder and two half adders to reduce the delay. Still CCSA suffers from high power consumption. In order to reduce the power consumption, the full adder used in CCSA with two multiplexers has been proposed. The proposed Montgomery modular multiplier has the capability to provide 26% average reduction in power when compared with previous designs.

Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

This work looks at optimizing finite impulse response (FIR) filters from an arithmetic perspective. Since the main two arithmetic operations in the convolution equations are addition and multiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniques should enhance the addition operation of the filter. The signed-digit number system is utilized to speedup addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also used here to compare its performance to the signed-digit adder. For multiplication, Booth encoding is used to reduce the number of partial products. The two filters are modeled in VHDL, synthesized and place-and-routed. The filters are deployed on a development board to filter digital images. The resultant hardware is analyzed for speed and logic utilization