Quantum computation based on Reciprocal Quantum logic

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.

Design infrastructure for Rapid Single Flux Quantum circuits

The primary operation of any processor is to perform basic arithmetic operations. In all basic arithmetic operations, multiplication consumes more time to be performed. Multiplier is the component which performs the multiplication operation. Its performance speed is going to affect the speed of the entire processing unit. The major operation of multiplier is to generate final product from partial products. To perform this major operation, the required architecture may require more area which intends to increase in latency in operation. In order to improve the performance of processor with minimum area, fast multiplier must be employed to perform multiplication operation. With high speed, the multiplier should occupy less area and consume low power. In the design of multipliers, a new technology called superconductor RSFQ logic is extensively used in order to achieve a multiplier design with less area and minimum latency in operation. From the time of introduction of this technology, different types of RSFQ multipliers are proposed. This paper gives an comparative analysis of rapid single flux quantum(RSFQ) technology multipliers like integer multiplier, matrix multiplier, parallel carry-save pipelined multiplier, floating-point multiplier in terms of area (number of Josephson junctions) and latency.KeywordsRapid single flux quantum (RSFQ)Josephson junctions (JJs)Integer multiplierMatrix multiplierParallel carry-save pipelined multiplierFloating-point multiplier

We review a new approach for digital architectures for software radio. Although direct digitization usually implies the simultaneous digitization of all channels in a particular band at a downconverted IF, we use this term to refer exclusively to the direct digitization of all bands, from near DC to RF. Furthermore, we present results on band selection and digitization of RF signals directly at the carrier frequency with high resolution. These novel approaches are enabled by a superconductor analog-to-digital converter technology using an ultra-fast IC logic known as Rapid Single Flux Quantum (RSFQ) logic, with performance capable of enabling envisioned software radios.

The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low- temperature 4 kA/cm', 1.75-pm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an %bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-I chips fabricated in 2001 are currently under testing at TRW.

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

We have developed and tested a classical superconducting logic interface to a qubit prototype based on two macroscopically distinct quantum states of a vortex in a long Josephson junction. The initial state preparation as well as the readout of a qubit is demonstrated by using a relatively simple Rapid Single Flux Quantum (RSFQ) circuit. RSFQ logic appears as a very feasible choice for constructing an interface between superconducting qubits and room-temperature electronics.

Rapid single flux quantum (RSFQ) electronics is characterized by a very low switching energy. This advantage leads to a noise susceptibility, which becomes a challenge for large-scale circuits as well as for circuits using Josephson junctions with reduced critical current density. We demonstrate an improved operation range and advanced noise immunity of basic cells resulting from an implemented phase shifting element. One of those elements is the π-phase shifter. It consists of a single flux quantum trapped in a superconducting loop. The π-phase shifter can be easily produced in standard niobium technology without any process modifications. Utilizing a mature process brings advantages concerning the reliable fabrication of complex circuits.

The gap between logic speed and memory access is a growing problem in all computing systems and it is exacerbated for ultra-high speed processors such as the proposed cryogenic Rapid Single Flux Quantum (RSFQ) logic working at 50 .100 GHz. The Superconducting Technology Assessment (STA) Panel considered two levels in a hierarchy of cryogenic memory located off of the processor chip. The first level of off-chip memory would be located on the MCM at 4 Kelvin (4 K) with the processor chip in order to minimize propagation-time delays. We are planning for a 1 Mb memory for this stage. The second-level memory would be much larger and could be located on a more efficient refrigerator stage at 40-77 K.

Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.

A half-adder (HA) and a full-adder (FA), using single-electron metal–oxide–semiconductor field-effect transistors (SE-MOSFET) hybrid circuits, are proposed. The proposed HA consists of three single-electron transistors (SETs), two enhancement-mode NMOSFETs and two depletion-mode NMOSFETs, and the proposed FA consists of four SETs, four enhancement-mode NMOSFETs, one enhancement-mode PMOSFET and three depletion-mode NMOSFETs. The total number of devices in the HA and the FA are 7 and 12, respectively. Compared with the conventional CMOS mirror FA with the 90 nm technology, the proposed FA can be constructed with 0.43 of devices and can operate with 5.6 of worst-case delay, 1/10.3 of average power consumption and 0.55 of power-delay product. The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are suitably determined. The basic operations of the proposed HA, HS, FA and FS have been successfully confirmed through SPICE circuit simulation based on the physical device model of the SET.

Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor role on most arithmetic circuits, performing some local optimisations but hardly improving the overall structure of arithmetic components. Architectural optimisations have been often studied manually, and only in the case of very common building blocks such as fast adders and multi-input adders, ad-hoc techniques have been developed. A notable case is multi-input addition, which is the core of many circuits such as multipliers, etc. The most common technique to implement multi-input addition is using compressor trees, which are often composed of carry-save adders (based on (3 : 2) counters, i.e., full adders). A large body of literature exists to implement compressor trees using large counters. However, all the large counters were built by using full and half adders recursively. In this paper we give some definite answers to issues related to the use of large counters. We present a general technique to implement large counters whose performance is much better than the ones composed of full and half adders. Also we show that it is not always useful to use larger optimised counters and sometimes a combination of various size counters gives the best performance. Our results show 15% improvement in the critical path delay. In some cases even hardware area is reduced by using our counters.

PurposeThe lack of reliable and scalable superconducting random access memory (RAM) cells is the main obstacle for full implementation of superconducting rapid single flux quantum(RSFQ) computers. This work points the methodology and the structures that shall be used in future implementation of RSFQ RAM.Design/methodology/approachA new design for RAM using two ferromagnetic strips in proximity to the superconductor in a RSFQ computer is presented (1). The concept of using a RAM RSFQ cell as a tuneable superconducting qubit is also explored.FindingsTwo basic architectures for superconducting RAM cells were developed with integration schemes in two dimensions.Research limitations/implicationsThe proposed RAM cells as depicted in Figures 7 and 16 offer smaller size and greater 3 scalability in comparison to other suggested schemes (4), (3), (2), (5).Practical implicationsCurrently, the main obstacle in implementation of RSQF computer is lack of reliable RAM cell. RSQF computer shall have potential to take a large fraction of classical supercomputers, as it consumes much less power.Social implicationsComputation power shall be cheaper when one uses RSQF computers for big data and computational centres. It is a matter of some time.Originality/valueThe publication presents the new design of superconducting RAM cell for use in RSQF computer. The numerical relaxation method is used to solve biharmonic Ginzburg–Landau equation. The analytic approach as a solution of a specified problem is given.

Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.