Experimental test of a superconducting digital interface for vortex qubits

Rapid single flux quantum (RSFQ) circuits are a promising technology for the post-Moore's law era. However, large-scale RSFQ circuits still suffer from low test yields. One major reason for the low test yield is the instability of process parameters, which can cause variations in the internal parameters of SFQ circuits, thereby leading to functional errors. Although some research teams have attempted to address parameter fluctuations from a design perspective or through process improvements to mitigate their impact, the lack of integration between design optimizations and process enhancements has resulted in still unsatisfactory test yields. This study proposes and validates a specific and practical multi-corner optimization design flow for RSFQ circuits to establish a positive feedback mechanism between process and chip design. This design flow enables the incorporation of process parameter variations at the design stage, thereby ensuring the circuit achieves expected performance. After fabrication, the predefined process corners can be used to quickly determine whether the chip batch falls within the testable range, while actual process information is continuously fed back to the design end for iterative optimization. To validate this flow, we performed a statistical analysis of process control monitor parameters from multiple batches of the SIMIT Nb03 process, identifying the corresponding process corners suitable for circuit design. Using this flow, we first optimized cell parameters to ensure sufficient bias margins across different corners, improving cells' robustness for large-scale circuits. We then designed a full adder and an auxiliary test circuit using this design flow and achieved 100% test yield with test results perfectly matching simulation results. Meanwhile, a pattern-matching circuit not using multi-corner optimization method demonstrated a counterexample with low test yield. Finally, we established digital models using timing parameters across different process corners to enhance the reliability of large-scale RSFQ circuit design.

The paper presents the determination of the high-frequency performance of Rapid Single Flux Quantum (RSFQ) circuits fabricated in superconductor-insulator-normal metal-insulator-superconductor (SINIS) technology. Circuits of different designs have been realized and were experimentally investigated, including specially designed T flip-flop (TFF) structures and circuits consisting of a switch terminated in Josephson transmission lines. For TFF circuits, the operational functionality was investigated in the frequency range from dc up to nearly 200 GHz. Two frequency domains were found. In the first domain, ranging up to frequencies of 80 GHz (f/sub C//spl cong/Y/sub C///spl Phi//sub 0/), correct digital operation of the device was ascertained. Beyond this range a second domain was found, ranging to nearly 200 GHz, for which quasi-analog frequency dividing is assumed. The bias current margins are /spl plusmn/30% at 40 GHz and /spl plusmn/15% between 130 GHz and 200 GHz. For circuits consisting of a switch, the operational functionality was proved in the frequency range from dc up to 50 GHz, with bias current margins of more than /spl plusmn/20%. The critical current density of the circuits is j/sub C//spl cong/750 A/cm/sup 2/. The smallest junction area is about A=12 /spl mu/m/sup 2/, and the characteristic voltage is V/sub C/=170 /spl mu/V.

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.

RSFQ impulse logic circuitry for future applications in high frequency metrology

Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.

The voltage multiplier (VM) is a principal component in high-precision digital-to-analog (D/A) converters based on rapid single flux quantum (RSFQ) circuits. Experimental confirmation of correct operation of the VM is important to guarantee the accuracy of the D/A converter. In this study, a circuit for direct comparison of the output voltages of VMs was designed and demonstrated. An on-chip SQUID sensor was utilized to detect the VM errors. Bit error rates of a single-stage VM were successfully measured down to 10/sup -12/ in the constant-voltage regions. A method of detecting errors during transients was also proposed and carried out.

We have simulated fluxon propagation within a Josephson transmission line that is one of the elements of a rapid single flux quantum (RSFQ) circuit. This line is a parallel connection of damped Josephson junctions coupled by superconducting inductances. Geometries with and without mutual inductances between neighboring cells are considered. If the time interval between two fluxons is less than 0.3 φ0Vc−1 (Vc characteristic voltage) a repulsion between them was observed. The repulsion sets a specific time delay between the fluxons that impose a rigid limitation for high frequency performance of RSFQ logic. The delay depends on the shunting parameter, bias current, and values of interconnecting inductances.

The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low- temperature 4 kA/cm', 1.75-pm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an %bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-I chips fabricated in 2001 are currently under testing at TRW.

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

The primary operation of any processor is to perform basic arithmetic operations. In all basic arithmetic operations, multiplication consumes more time to be performed. Multiplier is the component which performs the multiplication operation. Its performance speed is going to affect the speed of the entire processing unit. The major operation of multiplier is to generate final product from partial products. To perform this major operation, the required architecture may require more area which intends to increase in latency in operation. In order to improve the performance of processor with minimum area, fast multiplier must be employed to perform multiplication operation. With high speed, the multiplier should occupy less area and consume low power. In the design of multipliers, a new technology called superconductor RSFQ logic is extensively used in order to achieve a multiplier design with less area and minimum latency in operation. From the time of introduction of this technology, different types of RSFQ multipliers are proposed. This paper gives an comparative analysis of rapid single flux quantum(RSFQ) technology multipliers like integer multiplier, matrix multiplier, parallel carry-save pipelined multiplier, floating-point multiplier in terms of area (number of Josephson junctions) and latency.KeywordsRapid single flux quantum (RSFQ)Josephson junctions (JJs)Integer multiplierMatrix multiplierParallel carry-save pipelined multiplierFloating-point multiplier

Design infrastructure for Rapid Single Flux Quantum circuits

Rapid single flux quantum (RSFQ) electronics is characterized by a very low switching energy. This advantage leads to a noise susceptibility, which becomes a challenge for large-scale circuits as well as for circuits using Josephson junctions with reduced critical current density. We demonstrate an improved operation range and advanced noise immunity of basic cells resulting from an implemented phase shifting element. One of those elements is the π-phase shifter. It consists of a single flux quantum trapped in a superconducting loop. The π-phase shifter can be easily produced in standard niobium technology without any process modifications. Utilizing a mature process brings advantages concerning the reliable fabrication of complex circuits.

Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.