High-frequency performance of RSFQ circuits realized in SINIS technology

Rapid single flux quantum (RSFQ) circuits are a promising technology for the post-Moore's law era. However, large-scale RSFQ circuits still suffer from low test yields. One major reason for the low test yield is the instability of process parameters, which can cause variations in the internal parameters of SFQ circuits, thereby leading to functional errors. Although some research teams have attempted to address parameter fluctuations from a design perspective or through process improvements to mitigate their impact, the lack of integration between design optimizations and process enhancements has resulted in still unsatisfactory test yields. This study proposes and validates a specific and practical multi-corner optimization design flow for RSFQ circuits to establish a positive feedback mechanism between process and chip design. This design flow enables the incorporation of process parameter variations at the design stage, thereby ensuring the circuit achieves expected performance. After fabrication, the predefined process corners can be used to quickly determine whether the chip batch falls within the testable range, while actual process information is continuously fed back to the design end for iterative optimization. To validate this flow, we performed a statistical analysis of process control monitor parameters from multiple batches of the SIMIT Nb03 process, identifying the corresponding process corners suitable for circuit design. Using this flow, we first optimized cell parameters to ensure sufficient bias margins across different corners, improving cells' robustness for large-scale circuits. We then designed a full adder and an auxiliary test circuit using this design flow and achieved 100% test yield with test results perfectly matching simulation results. Meanwhile, a pattern-matching circuit not using multi-corner optimization method demonstrated a counterexample with low test yield. Finally, we established digital models using timing parameters across different process corners to enhance the reliability of large-scale RSFQ circuit design.

Bit error rate experiments in ring-shaped RSFQ circuits

Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

We have simulated fluxon propagation within a Josephson transmission line that is one of the elements of a rapid single flux quantum (RSFQ) circuit. This line is a parallel connection of damped Josephson junctions coupled by superconducting inductances. Geometries with and without mutual inductances between neighboring cells are considered. If the time interval between two fluxons is less than 0.3 φ0Vc−1 (Vc characteristic voltage) a repulsion between them was observed. The repulsion sets a specific time delay between the fluxons that impose a rigid limitation for high frequency performance of RSFQ logic. The delay depends on the shunting parameter, bias current, and values of interconnecting inductances.

We have developed and tested a classical superconducting logic interface to a qubit prototype based on two macroscopically distinct quantum states of a vortex in a long Josephson junction. The initial state preparation as well as the readout of a qubit is demonstrated by using a relatively simple Rapid Single Flux Quantum (RSFQ) circuit. RSFQ logic appears as a very feasible choice for constructing an interface between superconducting qubits and room-temperature electronics.

RSFQ impulse logic circuitry for future applications in high frequency metrology

The voltage multiplier (VM) is a principal component in high-precision digital-to-analog (D/A) converters based on rapid single flux quantum (RSFQ) circuits. Experimental confirmation of correct operation of the VM is important to guarantee the accuracy of the D/A converter. In this study, a circuit for direct comparison of the output voltages of VMs was designed and demonstrated. An on-chip SQUID sensor was utilized to detect the VM errors. Bit error rates of a single-stage VM were successfully measured down to 10/sup -12/ in the constant-voltage regions. A method of detecting errors during transients was also proposed and carried out.

Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 μW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.

Design infrastructure for Rapid Single Flux Quantum circuits

We have implemented a simple circuit of the rapid single-flux-quantum (RSFQ) logic family using a single-layer YBa2Cu3O7−x thin-film structure with 14 in-plane Josephson junctions formed by direct electron beam writing. The circuit includes two dc/SFQ converters, two Josephson transmission lines, a complete RS SFQ flip-flop, and an SFQ/dc converter (readout SQUID). Low-frequency testing has shown that the dc-current-biased circuit operates correctly and reliably at T∼30 K, a few degrees below the effective critical temperature of the junctions. Prospects for a further increase of the operation temperature and implementation of more complex RSFQ circuits are discussed in brief.

A vital precondition for the realization of rapid single-flux quantum (RSFQ) digital circuitswith reduced critical currents of the Josephson junctions is the implementation of anefficient technique for superconductive phase dropping. In this paper, we present a novelphase shifting element consisting of a miniature superconductive ring located over a groundplane hole. Contrary to the solutions reported up to now, this topology can be simplyintegrated within complex digital RSFQ circuits realized with conventional fabricationtechnology.