Bit error rate experiments in ring-shaped RSFQ circuits

The paper presents the determination of the high-frequency performance of Rapid Single Flux Quantum (RSFQ) circuits fabricated in superconductor-insulator-normal metal-insulator-superconductor (SINIS) technology. Circuits of different designs have been realized and were experimentally investigated, including specially designed T flip-flop (TFF) structures and circuits consisting of a switch terminated in Josephson transmission lines. For TFF circuits, the operational functionality was investigated in the frequency range from dc up to nearly 200 GHz. Two frequency domains were found. In the first domain, ranging up to frequencies of 80 GHz (f/sub C//spl cong/Y/sub C///spl Phi//sub 0/), correct digital operation of the device was ascertained. Beyond this range a second domain was found, ranging to nearly 200 GHz, for which quasi-analog frequency dividing is assumed. The bias current margins are /spl plusmn/30% at 40 GHz and /spl plusmn/15% between 130 GHz and 200 GHz. For circuits consisting of a switch, the operational functionality was proved in the frequency range from dc up to 50 GHz, with bias current margins of more than /spl plusmn/20%. The critical current density of the circuits is j/sub C//spl cong/750 A/cm/sup 2/. The smallest junction area is about A=12 /spl mu/m/sup 2/, and the characteristic voltage is V/sub C/=170 /spl mu/V.

We have simulated fluxon propagation within a Josephson transmission line that is one of the elements of a rapid single flux quantum (RSFQ) circuit. This line is a parallel connection of damped Josephson junctions coupled by superconducting inductances. Geometries with and without mutual inductances between neighboring cells are considered. If the time interval between two fluxons is less than 0.3 φ0Vc−1 (Vc characteristic voltage) a repulsion between them was observed. The repulsion sets a specific time delay between the fluxons that impose a rigid limitation for high frequency performance of RSFQ logic. The delay depends on the shunting parameter, bias current, and values of interconnecting inductances.

Rapid single flux quantum (RSFQ) circuits are a promising technology for the post-Moore's law era. However, large-scale RSFQ circuits still suffer from low test yields. One major reason for the low test yield is the instability of process parameters, which can cause variations in the internal parameters of SFQ circuits, thereby leading to functional errors. Although some research teams have attempted to address parameter fluctuations from a design perspective or through process improvements to mitigate their impact, the lack of integration between design optimizations and process enhancements has resulted in still unsatisfactory test yields. This study proposes and validates a specific and practical multi-corner optimization design flow for RSFQ circuits to establish a positive feedback mechanism between process and chip design. This design flow enables the incorporation of process parameter variations at the design stage, thereby ensuring the circuit achieves expected performance. After fabrication, the predefined process corners can be used to quickly determine whether the chip batch falls within the testable range, while actual process information is continuously fed back to the design end for iterative optimization. To validate this flow, we performed a statistical analysis of process control monitor parameters from multiple batches of the SIMIT Nb03 process, identifying the corresponding process corners suitable for circuit design. Using this flow, we first optimized cell parameters to ensure sufficient bias margins across different corners, improving cells' robustness for large-scale circuits. We then designed a full adder and an auxiliary test circuit using this design flow and achieved 100% test yield with test results perfectly matching simulation results. Meanwhile, a pattern-matching circuit not using multi-corner optimization method demonstrated a counterexample with low test yield. Finally, we established digital models using timing parameters across different process corners to enhance the reliability of large-scale RSFQ circuit design.

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 μW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.

RSFQ impulse logic circuitry for future applications in high frequency metrology

Various properties of stationary travelling waves propagating along a Josephson transmission line having positive nonlinear differential tunnelling conductance and distributed bias current are discussed geometrically in the state plane. First, the change of patterns of solutions in the state plane is uniquely determined for changes in conductance, fluxon velocity and bias current. Second, it is demonstrated that for the linear component of the conductance only, an event takes place in which the solitary wave velocity does not reach the velocity of the electromagnetic waves on a dissipationless transmission line in the certain limit of bias current. Finally, it is shown numerically that the non-linearity of the conductance has important effects on the waves, both quantitatively and qualitatively.

The voltage multiplier (VM) is a principal component in high-precision digital-to-analog (D/A) converters based on rapid single flux quantum (RSFQ) circuits. Experimental confirmation of correct operation of the VM is important to guarantee the accuracy of the D/A converter. In this study, a circuit for direct comparison of the output voltages of VMs was designed and demonstrated. An on-chip SQUID sensor was utilized to detect the VM errors. Bit error rates of a single-stage VM were successfully measured down to 10/sup -12/ in the constant-voltage regions. A method of detecting errors during transients was also proposed and carried out.

A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits

We have developed and tested a classical superconducting logic interface to a qubit prototype based on two macroscopically distinct quantum states of a vortex in a long Josephson junction. The initial state preparation as well as the readout of a qubit is demonstrated by using a relatively simple Rapid Single Flux Quantum (RSFQ) circuit. RSFQ logic appears as a very feasible choice for constructing an interface between superconducting qubits and room-temperature electronics.

Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

Timing jitter is an important factor in determining the limit of speed and scale of single-flux-quantum circuits. We estimated the timing jitter by a simple method using 2-bit shift registers. It was estimated by observing the transition between 1- and 2-mode operations while changing the bias current to the clock line. A sharp transition was observed in the shift register with a smaller number of Josephson junctions in the clock and data lines, suggesting the existence of a finite timing jitter. The timing jitter per Josephson junction was estimated to be 0.09 ps at a designed bias current. The temperature dependence supported that the timing jitter comes from thermal fluctuation.

Traveling-wave type solutions describing the fluxon motion on an infinite Josephson transmission line with shunt conductance and uniform bias current are derived analytically by approximating the sinusoidal current vs. phase-difference relation of the Josephson junction by a triangular saw-tooth like relation. From the result, the relation between the velocity of the waves and the bias current is obtained numerically, and the dependence of the phase and voltage upon space and time is also obtained. Finally, the energy flow of the waves along the line is expressed by a simple formula.

In the post-Moore era, slow-growing operating frequency and massive power dissipation make researchers seek new developing directions in integration circuits (ICs). The single flux quantum (SFQ) circuit, a type of superconducting digital circuit, is regarded as an alternative circuit for future computing technology. SFQ circuits are natural gate-level-pipelining synchronous sequential circuits requiring path balancing. However, path balancing may consume enormous resources, as the logic levels of fan-in gates of most gates are different, with the consumption originating from the extra gates (D-Flip-Flops, DFFs) for path balancing and the routing with a much larger clock tree. Hence, in this article, we propose a local optimization method to address the vast consumption problem of the clock tree caused by path balancing in SFQ circuits, primarily relying on self-developed electronic design automation tools for the JSICcomplier for SFQ circuits and using the SIMIT Nb03 cell library. Moreover, we design synchronizer IPs called Dsyn series to replace DFFs in path balancing. The clock nodes and the clocking path consumption are highly reduced by utilizing the proposed strategy, while the new series can be recognized as IPs and easily added to our library, affording scalability. Experiments in a demo S-box circuit demonstrated a percentage of Josephson junctions reduction in clock tree up to 36.48%, while on a few benchmark circuits, the corresponding results are up to 50.69%, demonstrating our method's effectiveness.