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In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data-processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.

Adders play a central role in arithmetic computations as well as digital signal processing. Besides addition, adders are used in multiple operations in processors. Based on our requirements upon variegated parameters our choice on adders can also be changed. Most digital systems, such as processors or computers, have 32-bit architecture, which includes 32-bit integers, registers, and memory locations, among other things. As a result, optimising 32-bit adders minimises total latency and thus enhances speed. In this work, performance analysis of 32-bit adders is compared by the Verilog programming language. 32-bit adder design is highly crucial as its architecture is widespread and used widely, and it is so hard to design. Designing several adders of 32 bit such as carry save adder (CSA), carry look ahead adder (CLA), ripple carry adder (RCA), modified carry select adder (MCSA), carry skip adder (CSKA), kogge stone adder (KSA) and carry select adder (CSLA), are explained in this work based on memory usage and delay. Discussions on adder types are made that aids in reducing the time usage on tedious tasks. CLA and CSKA were compared. Synthesis and simulation are done using Xilinx ISE tool. The simulation results help in the determination of the attributes that were assorted.

Carry select adder (CSLA) one of the fastest adders used in complex data processing to perform fast arithmetic functions. Minimum amount of power consumption is a major driving force behind the development of CMOS technologies. From the structure of CSLA it is clear that there is scope for reducing the area & power consumption in the CSLA. In this paper 8T full adder is used as a building block for 8-bit SQRT CSLA. 8T full adder is designed by XNOR-XNOR hybrid CMOS design. Based on this modification, 8-, 16-, 32-, 64-bit SQRT CSLA architecture has been developed & compared with the regular SQRT CSLA. Binary to Excess one converter (BEC) based CSLA are analyzed to study the data dependence & to identify all redundant logic operations. In this paper, all the redundant logic operations in the conventional CSLA are eliminated and a new logic formulation where carry select operation is scheduled before the calculation of final sum is proposed. Gate Diffusion Input (GDI) technique of low power digital combinatorial circuit design is also described. The frequency of operation is 5 MHZ. This work estimates the performance of the proposed design with the regular design in terms of area & power through the logic design & layout in 250nm CMOS process technology & implemented using Tanner (S-Edit) tool. The result analysis shows that the proposed structure is better than the conventional CSLA.

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

In digital systems design, the high-speed adders play an imperative role in modules like adders, multipliers, division, etc. to obtain the results quickly. In digital signal processor and computer data path circuits, carry look-ahead adder (CLA), carry save adder (CSA), carry select adder (CSeA) and carry skip adder are the mostly used fast adders to improve the performance of a system. This work mainly emphasizes on fault-tolerant carry save adder using hardware redundancy configurations for the betterment of reliability at the cost of area. The popular methods like dual (DMR) and triple modular redundancy (TMR) are implemented to detect only but not correct an error and tolerate single event upset (SEU) error respectively. To tolerate multiple errors, for example, two, three and four errors, the 5-modular (quintuple), 7-modular (septuple), and 9-modular (nonuple) redundancy configurations are used respectively. For experimental results, the implementation of a simple addition of four 4-bit numbers is considered on Altera FPGA EP4CE115F29C7 device using Quartus II synthesis software tool. Simulation results reveal that for example in nonuple MR, CSA using CSeA final stage obtain higher performance (45.7 MHz) with moderate power dissipation as 173.36 mW and at the cost of more LEs (216).

Parallel Adders or Ripple Carry Adders (RCA) are the building blocks of the digital processing units. However these RCAs have disadvantage of large propagation delay because of the propagation of carry from the first adder to the last adder. To overcome this drawback, Carry Look Ahead Adders (CLAA) are used. But again these CLAAs consumes more power because of use of large number of gates for generating carry. In this paper, we present a design of CLAA based on hybrid CMOS logic style which consumes less power as compared to the designs of CLAA based on complementary CMOS, Pass Transistor Logic (PTL) and Transmission Gate (TG). The proposed design of CLAA has less propagation delay as compared to its existing designs. Also the number of transistors required for the proposed design of CLAA are less as compared to the existing designs based on other logic style.

Most of the VLSI applications, such as DSP, image and video processing, and microprocessors use carry select adder (CSLA) for arithmetic functions. From the structure of regular SQRT CSLA, still there is possibility to obtain better design in which optimization of area, power are to be major concentrations along with high speed performance. One of the existing solutions used in SQRT CSLA is replacement of second level RCA by BEC. Though increases the performance, very less percentage of improvement in reduction of area and power dissipation. And also the existing adder with BEC technique is not suitable for low power applications. Hence this paper proposes Special Hardware using Multiplexers (SHM) design in place of second level RCA. It is observed from the results that the area and power dissipation are reduced at comparable percentages with respect to the RCA and BEC techniques. When SHM is used at the second level of second block in 16-bit SQRT CSLA, observed that area is reduced by 13.5% and power dissipation is reduced by 6.4%. This proposed logic is designed in transistor level using 0.12µm technology in the Micro wind tool.

This paper evaluates the performance of the gate diffusion input technique (GDI) on self-checking and self-resetting logic (SRL) GDI technique of carry select adder (CSA) and carry look-ahead adder (CLA) for different word lengths. In the proposed design adapting level restoration technique eliminates conductance overlap between n-MOS and p-MOS devices. The various self-resetting logic implementations for self-correcting of carry select adder and carry look-ahead adder can detect all single stuck faults in normal operation mode. Besides, two rail encoding technique is used in carry select adder are used for multiple error detection/correction. The SRLGDI setup consists of a pair of full adders, multiplexers, two rail checking, and self-resetting logic. In this technique, the self-checking carry select adder is used for reducing area and self-resetting improves the performance of the adder. The analysis of CSA and CLA with 180nm technology is simulated by using Cadence tools. The delay reduction is 12.836% for 8-bit CLA using SRL GDI, power reduction is 27.55% for 8-bit CSA using SRL-GDI compared to the gate diffusion input technique. This GDI technique implementation saves the average energy consumption up to 31.14% in CSA and 32.83% in CLA making it suitable for power optimization in high speed VLSI systems.

In electronic applications, better performance of the digital systems can be achieved using a faster adder circuit. This paper shows a modified carry-select adder (CSA) architecture which has low power and reduced area compared to the regular CSA. This high speed CSA is achieved by replacing the existing binary to excess-1 converter (BEC-1) with D-latch enabled CSA. Regular square-root CSA (SQRT CSA) architectures have also been developed and compared with the proposed BEC-1 D-latch enabled CSA. This work evaluates the performance of delay, area, power, and their products for existing and proposed CSA designs. This shows that proposed D-latch CSA structure is better than the regular and modified SQRT CSA and existing Ripple CSA. The proposed CSA architecture requires approximately 86 % fewer gates and 77 % shorter delay than the original CSA designs.

The speed of an adder is a significant factor in the performance for any arithmetic circuit. This paper primarily evaluates four different 4-bit adder architectures on 28nm technology in terms of speed. However, the performance of the adders is analysed based on delay, power dissipation, leakage current and area. The purpose of our work is to analyse the designs of the 4-bit adders, so as to give a better understanding as to which adder is suitable to the designer. The 4-bit adders, namely ripple carry adder (RCA), carry lookahead adder (CLA), carry skip adder (CSK) and Manchester carry chain adder (MCC), are designed using Cadence Virtuoso on 28nm technology. They are simulated and analysed at various supply voltages ranging from 0.6 to 1 V using ELDO tool. The results show that at 0.6 V CLA is faster than CSK by 27.9%, MCC by 8.2% and RCA by 26.46%.

This paper presents the concept, traits, principle and structure of 64-bit high speed VLIW microprocessor. The microprocessor facilitates 16 kinds of operational function. Out of these, our main focus is on the add operation. The add operation is implemented using 64-bit adders namely, Carry Look-ahead Adder, Carry Select Adder, Ripple Carry Adder, Weinberger Adder, Ling Adder and Modified CSLA using Ling Adders. These different processor architectures are then compared for Delay. It is observed that the architecture with Modified CSLA using Ling Adder incorporated is the fastest. The design is implemented Xilinx Virtex-7 FPGA, xc7vx690tffg1761-2 device and is simulated, synthesized and implemented with the help of Xilinx Vivado 2015.4 using Verilog HDL.

Based on the idea of sharing two adders used in the carry select adder (CSA), a new design of a low-power high-performance adder is presented. The new adder is faster than a ripple carry adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA.

In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and high-speed design utilizing a new add-one circuit that is used instead of the second ripple carry adder (RCA) with the input carry equal to one (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> =1) inside each group of the basic CSLA. Moreover, to expedite the add operation, a new grouping structure is proposed instead of the basic square-root (SQRT) grouping as well as utilizing a faster RCA in each group. Despite the fact that the proposed CSLA has not attained the lowest power consumption among all existing designs based on the PDK 45nm standard cell library, but it has achieved the lowest area and delay compared to previous CSLAs. Implementation results show that 8 to 33% area reduction and 12 to 44% speed improvement are achieved in the proposed CSLA compared to previous designs.

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.