Proposed high speed 64-bit VLIW microprocessor with modified adders

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

Adders are digital circuits that perform addition operation. There are various types of adder structures such as Ripple carry adder (RCA), carry look ahead adder (CLA) , carry select adder (CSLA) , carry save adder(CSA), carry skip adder, carry increment adder and so on. Again CSLA is of two types that is linear carry select adder (LCSLA) & square root carry select adder (SQRT CSLA). To design an efficient adder circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In this paper performance analysis of different adder structures like RCA, CLA, LCSLA and SQRT CSLA has been carried out and then a Heterogeneous adder structure is proposed, which compose of four different sub homogeneous adders (RCA, CLA, LCSLA and SQRT CSLA). The heterogeneous adder structure is used to demonstrate the tradeoffs between the speed and area. In this paper, all adder structures i.e., RCA, CLA, LCSLA and SQRT CSLA are to be designed and are to be compared with each other in terms of delay and area. Then by using the homogeneous adder structures different heterogeneous adder structures of 16-bit size are to be designed. Different heterogeneous adder architectures are compared with each other in terms of delay (ns) and area (number of LUTs). All the adder structures are designed using VHDL with the help of ISE Xilinx design suite 14.2 and functionally simulated using ISIM simulator. All the designs are to be synthesized using Xilinx XST synthesizer.

Adders play a central role in arithmetic computations as well as digital signal processing. Besides addition, adders are used in multiple operations in processors. Based on our requirements upon variegated parameters our choice on adders can also be changed. Most digital systems, such as processors or computers, have 32-bit architecture, which includes 32-bit integers, registers, and memory locations, among other things. As a result, optimising 32-bit adders minimises total latency and thus enhances speed. In this work, performance analysis of 32-bit adders is compared by the Verilog programming language. 32-bit adder design is highly crucial as its architecture is widespread and used widely, and it is so hard to design. Designing several adders of 32 bit such as carry save adder (CSA), carry look ahead adder (CLA), ripple carry adder (RCA), modified carry select adder (MCSA), carry skip adder (CSKA), kogge stone adder (KSA) and carry select adder (CSLA), are explained in this work based on memory usage and delay. Discussions on adder types are made that aids in reducing the time usage on tedious tasks. CLA and CSKA were compared. Synthesis and simulation are done using Xilinx ISE tool. The simulation results help in the determination of the attributes that were assorted.

In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data-processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.

This paper evaluates the performance of the gate diffusion input technique (GDI) on self-checking and self-resetting logic (SRL) GDI technique of carry select adder (CSA) and carry look-ahead adder (CLA) for different word lengths. In the proposed design adapting level restoration technique eliminates conductance overlap between n-MOS and p-MOS devices. The various self-resetting logic implementations for self-correcting of carry select adder and carry look-ahead adder can detect all single stuck faults in normal operation mode. Besides, two rail encoding technique is used in carry select adder are used for multiple error detection/correction. The SRLGDI setup consists of a pair of full adders, multiplexers, two rail checking, and self-resetting logic. In this technique, the self-checking carry select adder is used for reducing area and self-resetting improves the performance of the adder. The analysis of CSA and CLA with 180nm technology is simulated by using Cadence tools. The delay reduction is 12.836% for 8-bit CLA using SRL GDI, power reduction is 27.55% for 8-bit CSA using SRL-GDI compared to the gate diffusion input technique. This GDI technique implementation saves the average energy consumption up to 31.14% in CSA and 32.83% in CLA making it suitable for power optimization in high speed VLSI systems.

In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and high-speed design utilizing a new add-one circuit that is used instead of the second ripple carry adder (RCA) with the input carry equal to one (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> =1) inside each group of the basic CSLA. Moreover, to expedite the add operation, a new grouping structure is proposed instead of the basic square-root (SQRT) grouping as well as utilizing a faster RCA in each group. Despite the fact that the proposed CSLA has not attained the lowest power consumption among all existing designs based on the PDK 45nm standard cell library, but it has achieved the lowest area and delay compared to previous CSLAs. Implementation results show that 8 to 33% area reduction and 12 to 44% speed improvement are achieved in the proposed CSLA compared to previous designs.

The speed of an adder is a significant factor in the performance for any arithmetic circuit. This paper primarily evaluates four different 4-bit adder architectures on 28nm technology in terms of speed. However, the performance of the adders is analysed based on delay, power dissipation, leakage current and area. The purpose of our work is to analyse the designs of the 4-bit adders, so as to give a better understanding as to which adder is suitable to the designer. The 4-bit adders, namely ripple carry adder (RCA), carry lookahead adder (CLA), carry skip adder (CSK) and Manchester carry chain adder (MCC), are designed using Cadence Virtuoso on 28nm technology. They are simulated and analysed at various supply voltages ranging from 0.6 to 1 V using ELDO tool. The results show that at 0.6 V CLA is faster than CSK by 27.9%, MCC by 8.2% and RCA by 26.46%.

Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.

Central processing unit (CPU) is the brain of the computer, and arithmetic and logic unit (ALU) serves as the major component of the CPU. In ALU, for the addition of multiple bits, ripple carry adder (RCA) with carry select adder (CSA) configuration is used in this paper. These configurations require various blocks of full adders in cascaded form leading to enhanced area of the circuit. Therefore, this paper mainly focuses on reducing the area of such adders, so that implementation of ALU can be done in minimum space. Here, the area of 4-bit and 8-bit adders with CSA is designed and optimized in such a way that adders can improve the area consumption. The designing of the proposed adder is implemented in Verilog hardware description language (HDL) and simulated using ISIM simulator. It is synthesized and implemented using Xilinx ISE 14.7 by selecting Spartan 3E family and XC3S100E as the device. The proposed 4-bit adder and 8-bit adder reduces the area by 16.8 and 7.38%, respectively.KeywordsArithmetic and logic unitCarry propagation delayRipple carry adderCarry select adder

Parallel Adders or Ripple Carry Adders (RCA) are the building blocks of the digital processing units. However these RCAs have disadvantage of large propagation delay because of the propagation of carry from the first adder to the last adder. To overcome this drawback, Carry Look Ahead Adders (CLAA) are used. But again these CLAAs consumes more power because of use of large number of gates for generating carry. In this paper, we present a design of CLAA based on hybrid CMOS logic style which consumes less power as compared to the designs of CLAA based on complementary CMOS, Pass Transistor Logic (PTL) and Transmission Gate (TG). The proposed design of CLAA has less propagation delay as compared to its existing designs. Also the number of transistors required for the proposed design of CLAA are less as compared to the existing designs based on other logic style.

Based on the idea of sharing two adders used in the carry select adder (CSA), a new design of a low-power high-performance adder is presented. The new adder is faster than a ripple carry adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA.

Multipliers are important hardware components in most digital and high-speed systems, such as microprocessors, digital signal processors, and FIR filters. In reality, Multipliers, which are complicated units, are responsible for the total speed, size, and power consumption of digital systems. Multiplication in digital systems has a wide range of requirements for speed, size, power consumption, and other parameters. It comprises of partial product production, partial product reduction, and lastly carry-propagate addition. The Multiplier design focuses on minimizing power dissipation while still maintaining other parameters. To obtain considerable power savings in VLSI design, the dynamic power dissipation of multipliers must be reduced. The fundamental goal of this effort is to choose an appropriate adder that consumes less power, runs at a high speed, and is plainly less expensive. The available 8-bit adders, such as the Carry Select Adder, Ripple Carry Adder, Carry Look Ahead Adder, and Kogge Stone Adder, are investigated. Among the adders tested, the Kogge Stone Adder performs the best. This adder may be used to create efficient multipliers.

For continuous real-time monitoring of personal health, wearable devices are indispensable. The constraintsof cost, power consumption, and limited device dimensions are the critical issues which need to be handled carefullywhile designing these battery-powered devices. The wearables employ high-end processors dedicated for complex signalprocessing. The core of every digital signal processor is its data path. The arithmetic units like adders constitute thecore of data path and addressing unit. This work proposes a novel low-complexity asynchronous pipelined adder. Theproposed design guarantees great savings in power and latency, which makes it a suitable candidate for low-power high-speed sophisticated wearables. The proposed design consumes a minimum power of 33.46 ?W and offers a minimumpropagationdelayof 0.04ns incomparison tostate-of-artadders suchas ripplecarry adder(RCA),carry lookahead adder(CLA), and carry select adder (CSA). Thus, an area-delay-power efficient adder design guarantees high-end performancefor wearables.

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

Many processor architectures, such as digital signal processors and microprocessors, rely on arithmetic circuits. The efficient implementation and design of arithmetic units necessitates the creation of binary adder structures in a similar manner. A ripple carry adder has a tiny surface area yet is slower. Carry propagation is also one of the reasons why the total for each bit is generated sequentially after the preceding carry arrives. The primary idea behind this study is to replace the RCA in a normal CSLA with a binary to excess-1 converter (BEC) to achieve high speed, area efficiency, and low power consumption. The following architectures are implemented using Verilog HDL as a programming language, and their simulation results are also shown.KeywordsBinary to excess-1 converters (BEC)Carry select adder (CSLA)