Efficient FPGA Implementation Architecture of Fast FIR Algorithm Using Han-Carlson Adder Based Vedic Multiplier

Parallel FIR filters offer a powerful means of reducing the complexity of an FIR filter. This can be achieved with varying tradeoffs in the added latency. Unlike filtering based entirely on transforms whereby the latency exceeds the filter length, parallel FIR filters can operate with very low latency, while still offering significant reduction in the number of multiplications per output sample. Short transforms including the complex fast Fourier transform (FFT) and number theoretic transforms were originally proposed for use with parallel FIR filters. Though the complex FFT has been examined with limited gains for parallel FIR filters, number theoretic transforms (NTTs) have not been examined in detail. This paper presents results on using the NTT for parallel FIR filtering, which show significant benefits over the conventional decomposition techniques that use decimation factors that are powers of 2 and 3

Based on fast FIR algorithms (FFAs), this brief proposes new parallel FIR filter architectures, which are beneficial to symmetric convolutions of odd length in terms of the hardware cost. The proposed parallel FIR architectures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in the subfilter section at the expense of increase in adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area, and in addition, the overhead from the increase in adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a three-parallel 81-tap filter, the proposed structure saves 26 multipliers at the expense of five adders, whereas for a three-parallel 591-tap filter, the proposed structure saves 196 multipliers at the expense of five adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large.

Adaptive FIR filters are important in modern digital signal processing applications, and many situations require significant computational power attainable only through multi-processor configurations. Various block processing techniques have been proposed as viable alternatives to the sequential implementations to achieve the high throughput rate and reduce the effect of finite word length. While there are algorithm-based fault-tolerant techniques for protecting general digital signal processing systems against temporary/permanent failures, the specific features and requirements of the adaptive filtering systems have been largely ignored in the fault tolerance literature. By identifying common operations among different block adaptive filtering algorithms, however most operations of a particular algorithm can be protected with reasonably low-cost. We present a fine-grained approach, a highly efficient implementation of the well-known checksum encoding scheme, for protecting block adaptive filters. Through properly partitioning the input data, checksums for a parallel adaptive FIR filter can be calculated with reduced complexity. Computational and hardware overhead of the proposed scheme are analyzed, and shown to be proportional to the total number of partitioned submatrices.

Filters play a vital role in information and communication technology. This project proposes a less complexity FFA based parallel FIR filter design and implementation. This paper proposes the design of fast parallel filter with the block sizes L=2,3 and 4 respectively. By employing parallelism two or more number of samples are processed at each clock cycle which can be effectively used for multirate applications. The number of complex multiplications are reduced by employing polyphase decomposition. Here for all the cases, the overall filter output responses is decomposed in to several sub parts which includes sub filters and adders used before and after filters. The computational complexity is reduced for the fast parallel FIR filter when compared to the conventional parallel FIR filter. The simulation is done in Verilog with cyclone II family and EP2C70F672C6 device and EP2C35F672C6 device. The hardware implementation is done with Altera DE2 board and the results are reported. The results shows that the fast parallel filtering is efficient in terms of computational complexity

Based on fast convolution algorithm, this paper proposes improved parallel FIR filter structures for linear-phase FIR filters where the number of taps is a multiple of parallelism. The proposed parallel FIR structures not only use fast convolution algorithm to reduce the number of subfilter, but also exploit the symmetric (or antisymmetric) coefficients of linear-phase FIR filter to reduce half the number of multiplications in subfilter section at the expense of additional adders in preprocessing and postprocessing blocks. The proposed parallel FIR structures save a large amount of hardware cost for symmetric (or antisymmetric) coefficients from the reported FFA parallel FIR filter structures, especially when the length of the filter is large, e.g., the proposed 4-parallel FIR filter structure has eight subfilter blocks in total and four subfilter blocks contain symmetric coefficients, whereas the improved FFA structure has nine subfilter blocks in total and four contain symmetric coefficients. Specifically, for a 4-parallel 576-tap filter, the proposed design saves 144 multipliers (14.3%), 135 adders (10.2%) and 143 delay elements (11.1%).

Signal processing comes with a wide range of applications that includes enhancement of signal quality to improve accuracy and selection of required component from a received signal. As technology advances, signal processing systems has become more complex in which filters may operate in parallel. In such complex systems, there is a necessity for an efficient error tolerant implementation as reliability becomes critical. In this paper, a technique for error detection and correction is proposed which can detect and correct two errors by using a section wise single error correcting approach and the technique is explained in two approaches. Both approaches of technique can be applied in a parallel FIR filter configuration where filters use same response for same or different input signals. Thus, system homogeneity plays an important role in proposed technique for error detection and correction.

This paper proposes a hybrid class-AB/class-B voltage-controlled oscillator (VCO) with low voltage, low power, and a wide tuning range. The class-AB VCO core is designed to ensure robust start-up of the class-B VCO core. Featuring a high-efficiency class-B VCO core, the combination of class-AB/class-B VCO cores consumes low dc power. Based on the proposed architecture, the fabricated 0.18-μm CMOS VCO exhibits a measured tuning range of 25.6%. Operating at a low supply voltage of 0.75 V, the hybrid class-AB/class-B VCO cores consume a low total dc power of 2.4 mW. In this bias condition, the measured average value of phase noise for all frequency ranges is -101.4 dBc/Hz at 1-MHz offset from the carriers. Compared to recently published wide-tuning range VCOs, the proposed hybrid class-AB/class-B VCO simultaneously achieves a low supply voltage, a low dc power dissipation, and wide tuning range, leading to a good figure-of-merit including the tuning range (FOMT). In addition, the theories for analyzing the VCO are given in detail, and the mechanisms are validated by experiments.

Metal oxide semiconductor (MOS) devices are the basic building blocks for the logic circuits. Advancement in technology increases the expectation of customer in electronics. Various challenges face by IC designer during the uses of this Nano-scale technology because no one technology is completely satisfied all requirements. Better performance with minimum power dissipation and high stability is become basic need and low power dissipation is possible when power consumption of VLSI device is low. As the need of small electronics components and devices is increased day by day. There is a rapid growth in industry of electronics in few decades. World and technology are growing at the same speed. Day by day as the demand for small devices increases with high efficiency and result in flip-flop came into existence. These flip-flops have number of applications in electronics like used in communication, computers. As the size of the flip-flops decrease there is a problem of leakage current which prevents us to design a low power circuit. To decrease these leakage currents in the SR flip-flops and made it as a low power flip-flop an approach is used in this paper called as ON/OFF (ONOFIC). This ONOFIC implementation of SR flips decreases the leakage current and in this way our SR flip-flop is low power consuming

The following investigation on flip-flop circuits was originally undertaken to determine if a reliable flip-flop circuit could be designed to operate from a low supply voltage using tubes that are presently available and in production. The reason for designing the circuit to operate from a low supply voltage is to reduce the required power consumption of such information storage devices to a minimum and to provide a low d-c level output. The low d-c level output voltages of the two stable states of the circuit and the low flip-flop power dissipation enables an entire computer to operate from one regulated power supply rather than the numerous regulated supplies required by most computers. The low power dissipation is also essential since the reliability of germanium diodes and other heat sensitive components is greatly increased as their operating temperature is decreased.

A model of 4-bit multiplier having low power and high speed using Algorithm named Dadda is proposed here and the basic building block used is optimized Full adder having low power dissipation and minimum propagation delay. Full and half adder blocks have been designed using pass-transistor logic and CMOS process technology to reduce the power dissipation and propagation delay. The model has been designed using Tanner EDA in 90nm technology. The proposed multiplier starts its operation at the supply of 1V.

Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.

: Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or low-area techniques developed specifically for digital filters can be found in. Many applications in digital communication (channel equalization, frequency channelization), speech processing (adaptive noise cancelation), seismic signal processing (noise elimination), and several other areas of signal processing require large order FIR filters ,since the number of multiply - accumulate (MAC) operations required per filter output increases linearly with th e filter order, real - time implementation of these filters of large orders is a challenging task. This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter these methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to power consumption reduced thus reduce power consumption due to glitches is also reduced. This paper is implemented using XILINX ISE and hardware used is Spartan-3E and family is XC2S200E.

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

In Network-on-chip design two of the most important performance indices are the average delay of packets and power dissipation. The first depends on the level of congestion of the communication system, the second is strongly influenced by the power dissipated by the links of a network-on-chip (NoC) which accounts for a significant fraction of the overall power dissipated by the on-chip communication fabric. Such fraction becomes more and more relevant as technology shrinks. The selection policy of the output port in the NOC router with adaptive routing function affects both the performance and power dissipation. In fact, generally a NOC with a lower average delay has a lower power dissipation on the links for transmission. The selection policies proposed in the literature have the object or the minimization of the average delay or in some cases the reduction of power dissipation. In this paper we propose a selection policy aimed at minimizing both the average delay and power consumption of the communication system of NoC based architectures. The proposed policy uses a cost function obtained using a Fuzzy Rule Base System (FRBS) with two inputs an one output. Inputs are the level of use of the buffers of the downstream routers, and the link power dissipation of the selected output. The output of FRBS is the cost function. The experimental results, obtained using a cycle accurate NoC simulator for different traffic scenarios, shows that the proposed selection policy outperforms other selection approaches both in terms of average delay and in terms on power dissipation and energy consumption.

Low standby power dissipation is the primary need for most of the wireless applications for prolonged battery life. Traditionally ASIC solutions currently address either high density or high performance requirements and to some extent power to cater to the needs of a variety of customers. The solution needs to be improved further for the power considerations specifically. This paper describes how the ASIC solution for high density can be tuned to get a low power library. The strategy involves changing the length of all the mosfets in all the core cells in the library. This solution decreases the leakage power by at least 3X. This paper also describes about the performance and area impact of the low power library compared to the high density library. Unlike the other approaches such as multi Vt, this approach is very cost effective since it neither involves any changes in the fabrication process nor does it require extra masks and hence this is the most suitable and quick solution for the wireless applications.