Low Power Solution for Wireless Applications

This paper proposes a hybrid class-AB/class-B voltage-controlled oscillator (VCO) with low voltage, low power, and a wide tuning range. The class-AB VCO core is designed to ensure robust start-up of the class-B VCO core. Featuring a high-efficiency class-B VCO core, the combination of class-AB/class-B VCO cores consumes low dc power. Based on the proposed architecture, the fabricated 0.18-μm CMOS VCO exhibits a measured tuning range of 25.6%. Operating at a low supply voltage of 0.75 V, the hybrid class-AB/class-B VCO cores consume a low total dc power of 2.4 mW. In this bias condition, the measured average value of phase noise for all frequency ranges is -101.4 dBc/Hz at 1-MHz offset from the carriers. Compared to recently published wide-tuning range VCOs, the proposed hybrid class-AB/class-B VCO simultaneously achieves a low supply voltage, a low dc power dissipation, and wide tuning range, leading to a good figure-of-merit including the tuning range (FOMT). In addition, the theories for analyzing the VCO are given in detail, and the mechanisms are validated by experiments.

Parallel FIR filter is the need of many low power and high speed DSP applications. In this paper, fast FIR algorithm based parallel symmetric FIR filter using Han-Carlson adder based vedic multiplier is proposed. FFA algorithm reduces the multiplier count as compared to the traditional parallel design. In order to improve the performance of the proposed filter, recently developed Han-Carlson adder based Vedic multiplier is used. In the proposed design the adder unit is also implemented using Han-Carlson adder. In the proposed design two and three parallel FIR filters of order 24 and 72 are implemented using VHDL. The implementation results show that the proposed architecture provides low critical path delay and power dissipation as compared to the conventional one. With the advantage of low delay and power, proposed architecture is useful in modern signal processing and communication applications.

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.

Metal oxide semiconductor (MOS) devices are the basic building blocks for the logic circuits. Advancement in technology increases the expectation of customer in electronics. Various challenges face by IC designer during the uses of this Nano-scale technology because no one technology is completely satisfied all requirements. Better performance with minimum power dissipation and high stability is become basic need and low power dissipation is possible when power consumption of VLSI device is low. As the need of small electronics components and devices is increased day by day. There is a rapid growth in industry of electronics in few decades. World and technology are growing at the same speed. Day by day as the demand for small devices increases with high efficiency and result in flip-flop came into existence. These flip-flops have number of applications in electronics like used in communication, computers. As the size of the flip-flops decrease there is a problem of leakage current which prevents us to design a low power circuit. To decrease these leakage currents in the SR flip-flops and made it as a low power flip-flop an approach is used in this paper called as ON/OFF (ONOFIC). This ONOFIC implementation of SR flips decreases the leakage current and in this way our SR flip-flop is low power consuming

The following investigation on flip-flop circuits was originally undertaken to determine if a reliable flip-flop circuit could be designed to operate from a low supply voltage using tubes that are presently available and in production. The reason for designing the circuit to operate from a low supply voltage is to reduce the required power consumption of such information storage devices to a minimum and to provide a low d-c level output. The low d-c level output voltages of the two stable states of the circuit and the low flip-flop power dissipation enables an entire computer to operate from one regulated power supply rather than the numerous regulated supplies required by most computers. The low power dissipation is also essential since the reliability of germanium diodes and other heat sensitive components is greatly increased as their operating temperature is decreased.

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed ( \tau_{d} \sim 100 ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.

Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.

H.264 video applications based on mobile handheld devices are becoming more and more popular. How to protect the security has become an important topic. However, the significant power consumption of video encryption algorithms executing the limited battery capacity of handheld devices restricts the abroad use. In this paper, we propose a low power partial encryption scheme based on H.264, it combines the RC4 stream cipher, and encrypts intra 4 × 4 prediction mode, Intra 16 × 16 prediction mode, exponential-Golomb for MVD and level_suffix of CAVLC respectively. Experimental and analytic results show that the proposed method exhibits low power, low complexity and good security, and it hasn't effect on compression ratio. Moreover, it is suitable for secure mobile multimedia handheld products.

This paper presents a multi-objective optimization method for DC/DC converters used in More Electrical Aircrafts applications. Very high efficiency associated with high power density requires the use of wide bandgap devices, such as SiC semiconductors. Results show that, due to the use of SiC devices, the designed converter produces lower losses at hard-switching (HS) modulation than at soft-switching (SS) modulation. Furthermore, we show that there is an optimal number of small converters in parallel, which provides high efficiency even at low power as well as high reliability, compared to a single converter.

An ultra-low power neural spike sorting technique for implantable, multi-channel neural implant is proposed. It involves spiking neural network (SNN) with binary weights as an energy and area efficient classifier, along with a suitable frontend for spike encoding of the recorded neuro-potential. The proposed scheme employs two step training to implement supervised learning for the classifier, in order to achieve appreciable classification accuracy, along with low power dissipation. During the 1st phase a k-mean clustering module is trained with the real-time input data. In the 2nd phase, the trained means are used to perform supervised learning for the SNN classifier. After the training process, the low power SNN module is used for the classification task. In the proposed scheme, the K-means training module can be shared among large number of channels for training the dedicated SNN modules, which are relatively compact and can operate with ±4x lower power (as compared to the K-means sorter), while preserving the classification accuracy. Algorithm and architecture level optimizations for the proposed system are presented.

In order to remediate the very poor mineralization of paracetamol in water, even when well degraded by using a Non-Thermal Plasma (NTP) process at a very low dissipated power, a plasma-catalyst coupling process was tested and investigated. A homemade glass fiber supported Fe3+ catalyst was immersed in the liquid to be treated in a Dielectric Barrier Discharge plasma reactor. The plasma-catalysis process, at the same low dissipated power, achieved a mineralization rate of 54% with a full conversion rate of paracetamol at 25 mg L−1 in initial concentration after 60 min treatment, thanks to Fenton-like effects. The synergetic effects of the plasma-catalysis coupling process also improved the Energy Yield by a factor of two. The catalyst before and after use for treatment was characterized by Brunauer-Emmett-Teller and Thermogravimetric analysis. High-Performance Liquid Chromatography was used to measure the concentration of treated solution and to investigate the intermediates. Two of them, namely 1,4-hydroquinone and 1,4-benzoquinone, were formally identified. Some intermediates are presented in this paper as a function of treatment time and their UV absorbance spectra. NTP processes with and without catalyst coupling were compared in terms of acidity, conductivity, and nitrate concentrations in the treated solution.

Power efficient ultra-wideband based wireless communication for wireless body area network applications

The trend of decreasing device size and increasing chip densities involving several hundred millions of transistors per chip has resulted in tremendous increase in design complexity. Low power SRAMs are essential in today's demand as they are preferred as on chip memories with read write stability. The primary design challenge related to the conventional six-transistor (6T) memory cells is the conflicting set of requirements for achieving read data stability and write ability. The proposed seven-transistor SRAM cell for very high density and low power embedded applications as well as for stand-alone SRAM applications. It uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell. This paper presents a method based on multi-Vt to increase read, write stability and reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and it is also depend on Vt. The Cadence Virtuoso simulation in standard 45nm CMOS technology confirms all results obtained for this paper.

Switched-capacitor analog memories are well-suited to a number of applications where a continuous digitization of analog signals is not needed. In data acquisition systems based on the use of an analog memory, the input waveforms are sampled and stored at a high rate for a limited period of time, and the analog samples are then retrieved at a lower rate and digitized with a slow ADC before new waveforms are acquired. The advantages of using an analog memory are lower overall power dissipation and cost, higher density and reliability, and potentially superior performance. The analog memory essentially exploits the fact that the sampling and storage of samples in a bank of analog memory cells can be accomplished at a higher rate and with a greater precision than direct digital conversion. This dissertation examines the important components of an analog memory in detail and investigates their use in a number of architectures. The research has led to the design of an analog memory that can acquire analog waveforms at sampling rates of several hundred MHz with a dynamic range and linearity of more than 12 bits, without the need for elaborate calibration and correction procedures. This is accomplished by means of a new memory architecture that results in memory cell pedestals and sampling times that are independent of the signal level, as well as cell gains that are insensitive to component sizes. The write address control for this memory has been realized with an inverter delay chain that provides substantially higher performance with respect to sampling rate and timing accuracy than other published approaches. Based upon the concepts developed in this work, an experimental analog memory was designed and integrated in a 2-{mu}m CMOS process. Extensive measurements of this prototype at sampling rates up to 700MHz are presented and demonstrate a dynamic range, linearity, offset, and gain accuracy corresponding to a precision of more than 12bits after a simple dc baseline subtraction. One 32-cell channel in the experimental circuit dissipates only 2mW from a single 5-V supply.

FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS