FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS

Orthogonal variable spreading factor (OVSF) codes are standard in third generation UMTS cellular systems. The efficient generation of these codes is essential for reducing the area and power of wireless transceivers. In this paper, the basic properties of this family of codes are analyzed from an RTL perspective and two efficient hardware code generators are proposed. Tradeoffs and design solutions as well as low power considerations are discussed. These results represent the first reported implementation of an OVSF code generator.

This work reports about the system level design of a transmitter for the next generation of High-Speed Serial Interfaces (HSSI) to be implemented in a micro-controller for automotive Electronic Control Unit (ECU) applications, pushing the transmission speed up to 10 Gbps over a 10cm long cable. A voltage mode architecture is selected for low power considerations. We focus our analysis here on the system-level implementation of Feed-Forward Equalization as an FIR filter consisting of different transmitter slices driven by different bits in the data sequence. We consider different data rates and number of taps and analyze how the performance of the equalizer is affected by the quantization of the values of the taps in the practical implementation of the FIR filter.

Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However the long duration experiment on free-moving subjects is the current trend. For low power considerations, the compromise on sorting accuracy is made for the miniaturized and wireless neural recording ICs with a lower SR. In this paper, we introduce the cubic spline interpolation to strike the power and accuracy tradeoff on the recording microsystems for the off-site and on-chip spike sorter. According to the simulation results, the recorder operated with the SR of 12.5k sample per second (sps) outperforms the system with 25ksps SR on both accuracy and power if the interpolation is appropriately performed before the spike sorting.

Low standby power dissipation is the primary need for most of the wireless applications for prolonged battery life. Traditionally ASIC solutions currently address either high density or high performance requirements and to some extent power to cater to the needs of a variety of customers. The solution needs to be improved further for the power considerations specifically. This paper describes how the ASIC solution for high density can be tuned to get a low power library. The strategy involves changing the length of all the mosfets in all the core cells in the library. This solution decreases the leakage power by at least 3X. This paper also describes about the performance and area impact of the low power library compared to the high density library. Unlike the other approaches such as multi Vt, this approach is very cost effective since it neither involves any changes in the fabrication process nor does it require extra masks and hence this is the most suitable and quick solution for the wireless applications.

H.264 video applications based on mobile handheld devices are becoming more and more popular. How to protect the security has become an important topic. However, the significant power consumption of video encryption algorithms executing the limited battery capacity of handheld devices restricts the abroad use. In this paper, we propose a low power partial encryption scheme based on H.264, it combines the RC4 stream cipher, and encrypts intra 4 × 4 prediction mode, Intra 16 × 16 prediction mode, exponential-Golomb for MVD and level_suffix of CAVLC respectively. Experimental and analytic results show that the proposed method exhibits low power, low complexity and good security, and it hasn't effect on compression ratio. Moreover, it is suitable for secure mobile multimedia handheld products.

In order to cope with the existing shortcomings lie in hydrological monitoring areas, a novel hydrological monitoring system based on beacon-enabled ZigBee network is proposed in this paper. The designed monitoring system is made up of three parts: field collecting portion, field monitoring portion and remote service portion. The proposed data collecting station utilizes ZigBee for delivering field sensors' data to monitoring center, which is designed to collect, store, process and analyze the data and provide higher services to the hydrological department. The main idea about constructing a simple and effective beacon-enabled ZigBee network is presented. The improvement on Guaranteed Time Slot (GTS) assignment mechanism and low power consideration are also be involved. The practical results indicate the system is effective and reliable.

Nanoelectronics generally refers to nanometer scale devices, and to circuits and architectures which are composed of these devices. Continued scaling of the devices into the nanometer range leads to enhanced information processing systems. Generally, this scaling has arisen from three major sources, one of which is reduction of the physical gate length of individual transistors. Until recently, this has also allowed an increase in the clock speed of the chip, but power considerations have halted this to levels around 4 GHz in Si. Indeed, there are indications that scaling itself may be finished by the end of this decade. There are now pushes to seek alternative materials for nano-devices that may supplement the Si CMOS in a manner that allows both higher speeds and lower power. In this paper, I will cover some of the impending limitations, and discuss some alternative approaches that may signal continued evolution of integrated circuits beyond the end of the decade.

The purpose of this paper is to examine the impact of low statistical power on the process of research replication. The traditional model of interpreting the success of replication efforts emphasizes the results of statistical significance testing. Serious errors in the interpretation of replicated studies may occur if the focus is on only statistical significance. Correct interpretation of the probability of replication must include a consideration of statistical power and related factors such as effect size and type 2 error rates. Examples are provided illustrating the importance of power, effect size, and type 2 error rates in developing a scientific consensus based on repeated experimental trials. The establishment of an empirical consensus is essential to scientific progress and may be improved by the use of aggregated effect size, where the focus is on determining the degree of replication rather than a dichotomous decision based on the results of statistical significance testing. Consensus may be delayed if investigators continue to focus on the statistical significance of individual studies and ignore the effect size and statistical power of the investigations they conduct.

We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances abetter signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 mum CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 muW under +1.5 V supply.

DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips reduces power consumption but comes at a performance penalty to return to full power for servicing requests. We propose a novel cache replacement policy and write buffer that prevents cache blocks going to certain DRAM chips from being replaced, resulting in less requests going to these chips, and allowing them to remain idle for longer periods of time. Our proposed modifications improve DRAM energy efficiency by 10% on average (up to 30%) compared to a base case that utilizes low power modes, and by 76% compared to a base case that does not utilize power saving modes.

A test strategy for testing NoC switches based on flooding is presented in this paper. This test strategy tests all switch ports and network routes, while it avoids sending a test packet arriving at a switch in every direction. This test strategy is referred to as pseudo-exhaustive, versus the exhaustive testing that sends an incoming test packet of a switch in every direction. As compared with the exhaustive strategy, the pseudo- exhaustive testing consumes lower power consumption, has a lower test time and still has 100% switch port fault coverage. This paper discusses our test strategy, test mode switch hardware requirements, and evaluates test power, time, and coverage.