LSI processing technology for planar GaAs integrated circuits

Photoresist processing has been shown to contribute significantly to device yields in integrated circuit manufacturing. Primary factors in photo-resist processing are dimensional reproduction of photomask geometries, sensitivity to environmental and process conditions, and etch protection afforded by the photoresist. These factors are discussed relative to device yield. A series of scanning electron micrographs are presented which attempt to show the importance of adequate photoresist protection in integrated circuit processing. The unique capabilities of a positive photoresist are related to the factors which have the greatest impact on yield: dimensional reproducibility or fidelity, etch protection and tolerance to processing and environmental factors. The role of photoresist processing and its impact upon device yield has been clearly established in integrated circuit manufacturing. The imaging characteristics of a photoresist material plays a vital role in maintaining and improving device yields. Selection of a photo-resist material should, therefore be based upon imaging properties that fulfill the needs for improved device quality and yield. These properties are defined below:

Two techniques for dry etching of sol-gel lead zirconate titanate (PZT 52/48) thin films were investigated: reactive ion etching and argon ion milling. Etched profiles were characterized by scanning electron microscopy. For reactive ion etching, a parallel plate etcher was used with HC2ClF4, an environmentally safe etch gas, in a process described by other researchers. Etch rates were measured and compared as a function of electrode shield material (ardel, graphite, alumina) and RF input power (100 to 500 W). These etch rates varied from 10 to 100 nm/min. Reactive ion etched sidewall angles 12° off normal were consistently produced over a wide range of RF powers and etch times, but overetching was required to produce a clean sidewall. For argon ion milling, a 300 mA/500 V beam 40° off normal to the substrate operating in a 72 mPa argon pressure was used. These ion milling conditions produced an etch rate of 250 nm/min with a sidewall slope angle of about 70°. The ion milling etch rate for sol-gel PZT was significantly faster than rates reported for bulk PZT. The 500 nm thick PZT films used in this study were prepared by the sol-gel process that used methoxyethanol solvent, spin coating on t/Ti/SiO2 silicon substrates, and rapid thermal annealing for 30 s at 650 °C for crystallization of the perovskite phase.

The gate length of GaAs MESFETs is required to be shorter for higher microwave frequency applications. The side-wall process using silicon nitride is one of the effective processes to fabricate short gate length GaAs MESFETs. The side-wall process consists of deposition and anisotropic etching of silicon nitride and delivers plasma induced damages on the channel layers of the devices. In this study, the effects of plasma induced damage on the channel layers of ion implanted GaAs MESFETs during reactive ion etching and plasma ashing processes have been investigated. The plasma induced damage was characterized by sheet resistance measurement, Xray photoelectron spectroscopy(XPS) and auger electron spectroscopy(AES) of different etched surfaces, compared with a chemically wet-etched reference surface. Also the effect of the plasma induced damage on the device performance was investigated. As a result, plasma ashing can deteriorate the plasma-induced damage by RIE.

From measurements of optical emission and silicon etch rate, we are able to separate contributions due to the chemical etching and the ion-bombardment enhanced etching in the CF4+O2 reactive ion etching process. The chemical etching part of undoped polysilicon etch rates is linearly proportional to the ground state fluorine population and the ion bombardment part is proportional to the dc self-bias voltage (V2.3bi). The chemical etching predominates during plasma etching, giving rise to the isotropic etch profile, while both the chemical etching and the ion-bombardment enhanced etching mechanisms coexist during reactive ion etching. A degree of the etch anisotropy in reactive ion etching is determined by competition between the chemical etching and the ion-bombardment enhanced etching, and can be expressed by an equation which only involves two physical quantities, etch rate and fluorine concentration, experimentally measurable in plasma etching and reactive ion etching. The silicon loading effect leads to a substantial decrease in a number density of the ground state fluorine and consequently makes an etch profile more directional by reducing a contribution due to the chemical etching. Also, we have identified important process parameters which influence etch profiles.

1. Introduction Ge has been received much attention as the next generation semiconductor materials due to its attractive characteristics such as high carrier mobility[1] and narrow bandgap corresponding near infrared wavelength[2]. In order to utilize its characteristics for the applications, Ge-on-Insulator (GOI) structure is necessary. Several fabrication methods for GOI have been suggested such as wafer bonding and mechanical thinning[3], Smart-CutTM[4,5], and SiGe condensation[6]. It is well known Smart-CutTM is widely used for commercial Si-on-Insulator (SOI) fabrication. However, Ge is more sensitive to damages caused by ion implantation and difficult to recover damages completely. Therefore, the best way for GOI fabrication have not been developed.In early stage of SOI R&D, many approaches were proposed, too[7]. Wafer bonding and etchback is one of the simplest technique, and the advantage of this method is any damages due to ion implantation or mechanical stress are not induced to the top semiconductor layer. Therefore, we focused on etchback technique for GOI fabrication. It is necessary to develop appropriate Ge etching method with moderate etching rate and keeping or improving surface flatness. In this study, we aim to develop appropriate etching method of Ge for etchback GOI fabrication. 2. Experimental and results We used single side mirror polished Ge wafer with a thickness of 500 μm. Figure 1 shows the experimental procedure in this study. The original polished top surface was covered by photoresist to avoid etching from this side. Firstly, we confirmed HF + HNO3 mixture solution for Ge etching because it is widely known as etching solution for Si. Figure 2 shows optical microscope images for the back side (non-polished side) of (100)-oriented Ge wafer (a) before etching and (b) after etching by HF + HNO3 for 7 minutes. By etching, surface uniformity drastically improved. So, wet etching can be used for Ge thinning and planarization. However, this solution reacts handle Si substrate of GOI, too. As an alternative etching solution, we selected HF + H2O2 mixture[8]. Figure 3 shows the etching result of (100)-oriented Ge etched by HF + H2O2 + H2O (7:7:6) solution. Although Ge was etched similar to Fig. 2(b), surface uniformity was inferior to HF + HNO3 etching. To improve surface uniformity, CH3COOH was added as diluent instead of H2O because politic amount of CH3COOH into HF + HNO3 solution leads isotropic etching and mirror plane on Si surface[9]. Figures 4 shows the etching results of (100)-oriented Ge by HF + H2O2 + CH3COOH (1:1:1) solution. Surface uniformity improved than Fig. 3 and there is no orientation dependence (data not shown). Therefore, isotropic etching occurs on Ge surface. The average etching rate in the first 20 minutes calculated from the lost masses was 7.9 μm/min. It should be noted any agitation was not carried out during etching and longer etching time leads decreasing of etching rate. Possible etching reaction is expressed as[10]:2CH3COOH + 2H2O2 → 2CH3COOOH + 2H2O (1)Ge + 2CH3COOOH + 2e - → Ge2+ + 2CH3COO- + 2OH- (2)As further investigation of surface uniformity, atomic force microscope (AFM) observation was carried out. Figure 5 shows AFM images for backside of (100)-oriented Ge etched for 110 minutes. The RMS of 30×30 μm2 area is 0.48 nm. Compared with the RMS of original backside (> 5 μm), the surface flatness is improved drastically. In the conference, electrical characteristics of etched surface will be presented. 3. Conclusions For etchback GOI fabrication, we study isotropic etching for Ge. HF + H2O2 + CH3COOH mixture solution can etch Ge isotropic and improving surface uniformity. This solution has a potential as etching solution for etchback to make GOI structure. Acknowledgements This work was supported by JSPS KAKENHI Grant Numbers 19K15028 and 19H05616. Appendix Original concentrations of the chemicals in this study are HF: 49 wt%, HNO3: 69 wt%, H2O2: 30 wt%, and CH3COOH: 99.7 wt%. All compounding ratios in this article are volume rate.

Two-capacitor matching properties for digital to analog (DA) and analog to digital (AD) converters were evaluated by using different etchers. The etching step for forming the upper layer was carried out by: (i) a barrel plasma etcher, (ii) a downstream plasma etcher, and (iii) a parallel-plate reactive ion etcher (RIE). Matching errors processed in the barrel and downstream etchers with isotropic etching characteristics were 0.38% and 0.15% in full scale, respectively. The error processed in the downstream etcher was 40% of that processed in the barrel etcher. It is estimated that the improvement in the down-stream etcher is caused by better uniformity and a smaller coefficient of lateral etching. The matching error processed in RIE was 0.096% in full scale and 62% of that processed in the downstream etcher. RIE with the anisotropic etching characteristic can minimize the lateral etching. Therefore, RIE decreases the error caused by the nonuniformity of the etching rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Polishing and cross-sectioning of integrated circuits is standard practice in failure analysis. With most integrated circuit defects, all that is usually needed is mechanical polishing to the cross-sectioned plane of interest. The sample is then ready for examination in the scanning electron microscope (SEM). However, some defects are too small or too subtle to be seen without delineating them in some way. Chemical etching is useful in many situations but sometimes does not highlight the defect and may introduce artifacts. In this experiment, cross-sectioned chips were ion milled for a short period to highlight or uncover defects.After locating failing transistors, samples were cross-sectioned on diamond paper using the open block method (i.e., not encapsulated in epoxy). A special ion mill sample holder was designed to accommodate the polishing fixture. This holder is inserted into the ion mill. (This eliminates the need to transfer the chip from one fixture to another, avoiding damage or contamination.) Samples were milled in a Gatan ion mill for an initial period of two minutes at a 20 degree tilt. A current of ˙5 mA and voltage of 5 kV were used. Samples were positioned so that maximum milling occurred in the area of the failing transistors.

Observation of anomalous high resistance to implanted areas caused by reactive ion etching (RIE)

Up until the late 1960s, chemical etching, also called wet solvent etching, was the key technology to integrated circuit manufacturing. Indeed, from the standpoint of manufacturing, wet etching provides low cost and often infinite selectivity. But, inherent limitations in wet etching preclude the use of this technique for micron and submicron pattern sizes. The most serious limitation is that of isotropic etching, which results in undercutting of the mask material and hence limits the minimum size of the pattern. To obtain high-density packing of microelectronic circuits, anisotropic etching is essential. By the early 1970s, CF /02 dry etching was widely adopted for patterning. It was widely recognized that dry etching offered the possibility of a vertical etch rate that greatly exceeded the horizontal etch rate (namely anisotropic etching). As a result, these dry etching techniques, which can generate anisotropic etch profiles, came into prominence. Dry etching soon began to appear in IC fabrication. However, these dry etching technologies, like wet processes, had their resolution limited by undercutting, and other, even more anisotropic etching techniques appeared. Among these were reactive ion etching (RIE). The RIE technique which has been widely adopted for IC fabrication until now provides moderate selectivity, etch rate and high anisotropy. In the mid-to-late 1970s, research began on a dry etch technique which would combine the positive features of RIE with directional bombardment of the surface by ions accelerated through electrostatic sheaths. Figure 1.1 shows how integrated circuits have evolved and how the number of individual components per circuit has increased with time. It is seen in the figure that the component density of IC circuits has doubled every year and this yearly doubling rate has been maintained from the first IC in 1960 until recently. At the same time, the design feature size has shrunk from 6 μm to 0.8 μm in the last 15 years, and the smallest dimensions are expected to decrease to 0.1 μmin the near future.

Plasma etching or Reactive Ion Etching (RIE) is the workhorse for patterning of semiconductor devices since the early 1980-ies when it replaced wet etching in manufacturing. Today, RIE is reaching levels of performance which were unimaginable back then. At the same time, etching technologies such as Atomic Layer Etching (ALE), radical, dry vapor and Ion Beam Etching are finding their way into manufacturing for certain applications. We will present an overview of dry etching technologies used in semiconductor manufacturing. The emphasis is on the elementary surface processes and how they impact the performance on the wafer. We will start from less complex etching technologies which use just one kind of etching species, such as neutrals, radicals or ions. Then we combine these techniques into cycling processes which leads to the discussion of ALE. The highest level of complexity is reached in RIE with simultaneous species fluxes. Reactor designs for the various etching technologies and process control will be covered. Finally, and an outlook into the future of semiconductor device etching will be given.

Anisotropic etching of titanium silicide is essential if its low resistivity gate properties are to be utilized on scaled MOS devices. and plasmas, as well as ion milling, were used to etch composite titanium silicide/polysilicon films, with each displaying definite drawbacks. plasmas yielded rough etching and etch residue, presumably due to the high oxygen content of the silicide film and the relatively high selectivity (low oxide etch rate) of the etch. reactive ion etching and ion milling produced smooth etching but lacked the selectivity to stop on thin underlying gate oxides. A combination of these processes, however, provided successful anisotropic patterning of such structures. A nonselective, smooth etching reactive ion etch was used to etch through the silicide layer, followed by a higher selectivity plasma etch through the underlying polysilicon down to the thin gate oxide.

This chapter introduces plasma etching—an extensive and perhaps the most widely used micro- and nanoprocessing method both in industry and in research and development laboratories worldwide. The emphasis is on the practical methods in plasma etching and reactive ion etching when used for submicron and nanoscale device fabrication. The principles of plasma etching and reactive ion etching equipment for sample fabrication will be introduced.

Electrodes used for neural interfaces are typically encapsulated by biocompatible materials such as Parylene-C. Tips of a Utah electrode array (UEA) for recording neural action potentials are typically exposed using a reactive ion etching (RIE); however, it has limitations due to the complex 3D geometry of electrode arrays, resulting in nonuniformity of deinsulated area, difficulty in achieving very fine tip exposure, and decrease in selectivity in acquiring the neural signals. The laser ablation technique can be used to deinsulate electrode tips with exposures smaller than 20 µm. However, the electrode arrays suffer from increased impedance due to redeposition of the carbon debris produced by the ablation of the Parylene-C on the active area of the electrodes. The hybrid laser and plasma etching uses a laser (KrF) ablation followed by an oxygen reactive ion etching process to better control tip exposure, particularly for electrode arrays with more complex geometries, and a lower electrode impedance at the same time. Characterization of the deinsulated electrode surface by scanning electron microscope (SEM), x-ray photoelectron spectroscopy (XPS) and impedance of a Utah electrode array (UEA) suggests that the hybrid laser/RIE method is suitable for deinsulation of UEAs for neural interface applications.

The effects of chemical, plasma, and reactive ion etching (RIE) treatments on the adhesion of Cu and Cr/Cu to the multifunctional polymer were investigated. The adhesion was measured with the newly developed pull test. The polymer surfaces were characterized by the x-ray photoelectron spectroscopy, atomic force microscopy, and surface free energy measurement. The failure modes were examined with the scanning electron microscopy and energy-dispersive spectroscopy. It was found that the adhesion of Cu and Cr/Cu to the highly functional photoresist was poor, regardless of the chemical, plasma, and reactive ion etching treatment with either O2 or CF4 used. However, the RIE pretreatment with the gas mixture (O2+CF4) of the photoresist surface increased the adhesion of sputtered Cr/Cu to the photoresist remarkably, and the failure mode was cohesive within the photoresist. Furthermore, the RIE pretreatment with pure oxygen gave rise to the needle-like surface together with virtually no introduced reactive functional groups, whereas the RIE with O2-rich gas mixture of O2+CF4 resulted in the relative smooth polymer surfaces and the newly formed C=O/O–C–O and O–C=O functionalities were incorporated on the treated surface with the increased polar surface free energy. The adhesion mechanism based on the experimental adhesion results and the surface characterizations of the polymer is proposed and discussed.

High density plasma sources are becoming an industry standard for plasma etch tools. They provide enhanced etch rates and improved productivity as well as a wider process space compared to reactive ion etch (RIE) or magnetically enhanced RIE (MERIE) technology. As the complexity of metallization for IC interconnects increases, and as the critical dimension (CD) of advanced devices decreases, high density plasma etch systems are best suited to meet metal etch process requirements. The Decoupled Plasma Source (DPS) metal etch chamber was used at Motorola to develop processes for advanced Al-1%Cu logic devices. Through design of experiments (DOEs) and single variable experiments, general process trends were defined. In particular, the influence of the process parameters on residue removal, profile and CD control are detailed, and possible mechanisms are outlined. The kinetics of the process, as reflected by the etch rate in the main etch step and the duration of the over etch step is also examined. The results suggest that robust, manufacturable, and high productivity processes can be developed for the DPS metal etch reactor for a wide range of devices. This is best achieved by thoroughly characterizing the mechanisms underlying the process trends and by applying this knowledge to optimize the traditional metal etch metrics relevant to devices performance and reliability.