Introduction

Background: CR-39 nuclear track detectors are widely used in various fields, including science, technology, astronomy, and environmental preservation, to detect and register heavy ions, neutrons, and alpha particles. Objective: This study aims to determine the optimal etching duration for CR-39 nuclear track detectors by comparing etching methods: The wet etching (using a water bath) and the dry etching technique (using dielectric barrier discharge (DBD) plasma). Methods: The traditional etching method involved immersing CR-39 detectors in a sodium hydroxide (NaOH) solution at 70 °C for varying durations. The dry etching method employed employs a non-thermal DBD plasma system to etch solid-state nuclear track detectors (SSNTDs) without the use of chemical solutions. Results: Photomicrographs revealed that tracks from chemical etching became clearly visible after 1 hour and developed at 5 hours. In contrast, the dry etching technique was significantly faster; tracks began to appear after just 1 minute of DBD plasma etching and were fully developed at 5 minutes. The optimum track density for DBD plasma was 20340±56 tracks/mm2 at 3 minutes, whereas the traditional water bath method achieved an optimum track density of 5238.0±5.7 tracks/mm2 at 2 hours. The shorter etching duration in the dry method likely facilitates the emergence of latent tracks without overlap. Conclusions: The bulk etch rate (VB) for CR-39 detectors using the dry DBD plasma etching technique was faster compared to the traditional chemical etching method. This demonstrates the efficacy of the dry etching process in significantly reducing etching time required for etching SSNDs.

The important role of reactive ion etching (RIE) technique is to etch the semiconductor surface directionally. The purpose of the current research is to fabricate polysilicon micro-gap structures by RIE technique for future biosensing application. Therefore zero-gap microstructure of butterfly topology was designed by using AutoCAD software and finally the designed was transferred to commercial chrome glass photomask. Ploysilicon wafer samples were selected to achieve high conductivity during electrical characterization measurement. The fabrication process starts from samples resist coating and then by employing photolithography through chrome glass photomask the zero-gap pattern of butterfly topology was transferred to resist coated sample wafer followed by resist stripping from exposed area and finally by reactive ion etching (RIE) technique the open area of polysilicon was etched directionally at different etching time to fabricate micro-gap structure on wafer samples. The spacing of fabricated micro-gap structures will be further shrink by thermal oxidation (size reduction technique) until to nanosize gap spacing. The proposed nanospacing gap will definitely show the capability to detect the bio molecule when inserted into the gap spacing.

Silicon etching is a process that is regularly employed in the semiconductor industry for many applications ranging from micromachining on the sub-millimeter scale to intricate pattern formation in tens of nanometer regime. Wet etching is used for bulk silicon removal. Such etching processes, generally, involve multiple chemical reactions where a liquid solution of etching agents removes surface atoms of silicon through chemical or electrochemical redox reactions at the substrate-etchant interface. Many wet etching processes are anisotropic, and thus the wet etching of silicon with hydroxide solutions tends to be direction or crystalline plane specific, allowing for directional control and reduced undercutting of any etch mask. An additional advantage of metal hydroxide etchants rise from their selective nature of extremely poor etch rate towards the basic oxide of silicon. This makes growing the hard mask of SiO2 a very cost effect step in the wet etching process. NaOH and KOH solutions are well known wet etching agents that offer inexpensive alternatives to anisotropic dry etching but are often either difficult to control (etch rate-wise) or result in rough etched surfaces. Only through better understanding of the chemical reaction mechanisms, i.e. the role of alkali metal cations and water molecules during the wet etching process more controllability and desired etch surface profiles can be achieved. This study summarizes the results from a series of wet etch processes with all the five different group 1 alkali metal oxides and discusses in detail how different types of group 1 metal ions impact the dynamics of the chemical reactions in the aqueous medium. Wet etching assisted by smaller cations like Li+ tend to be more controllable while larger cations like Cs+ result in much faster etch rates. Surfactants added to fast etching metal hydroxides result in finer sidewalls and smoothened etched surface on silicon. Later in the paper, the effect of microwave irradiation on the surface tension, structural arrangement of water molecules and its application in anisotropic etching are highlighted. Step by step details of the experiments are provided in the materials and methods section making the study easy to understand. Line profile plots, optical images, SEM micrographs and XRD intensity plots are presented throughout the report to support the given explanations. Research findings from the study experimentally establish a trend for anisotropic etch rates of silicon substrate with aqueous solutions of all the group 1 alkali metal hydroxides. Silicon etch rate increases down the group.

The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely the wet chemical etching method, using HNO3-HF-CH3COOH solution, and the Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching using inert gas only (e.g., argon gas), and ion chemical etching using an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning microscope (OSM) and Joel Scanning microscope (JSM). The formed hole width (ω) increases by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about ( 0.0707 and 0.0537 µm/min ) .Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. Normal 0 21 false false false MS X-NONE X-NONE The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely wet chemical etching method, using HNO3-HF-CH3COOH solution, and Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching used inert gas only (e.g., argon gas) while ion chemical etching used an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning Microscope (OSM) and Joel Scanning Microscope (JSM). The formed hole width (ω) increased by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about (0.0707 and 0.0537 µm/ min). Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

: A microcavity surface emitting (SE) laser is very attractive for future optoelectronic applications such as optical parallel processing and optical interconnections. In order to realize such a low threshold SE laser, micro-fabrication providing a low damage etch is one of important issues. We have introduced a reactive ion etch (RIE) and reactive ion beam etch (RIBE) technique to fabricate a tiny dielectric multilayer reflector and micro-resonator for surface emitting lasers. In most of SE laser structures, a SiO2/TiO2 dielectric multilayer reflector or semiconductor multilayer mirror is used as high reflective mirrors. However, it has been difficult to fabricate the microcavity with steep side walls by wet chemical etching since each material has different etching rates. Dry etch techniques for multilayer structures, especially for GaInAsP/InP semiconductors, have not been fully studied.

As transistor geometry shrunk and System on Chip (SoC) requirement increased, chips with multiple operation voltages become regular criteria in IC design specification. It means multiple gate oxide thicknesses have to be integrated in semiconductor manufacturing front-end-of-line (FEOL) process. However, process thermal budget will be one of the concerns of transistor electrical performance shift resulted from diffusion of implantation species. In this study, thicker gate oxide (MV) was etched back by wet chemical as thinner gate oxide (I/O) to reduce gate oxide formation thermal budget. However, wet etching rate was degraded after clean and lithograph sequential processes. The oxidant, in wet clean chemical, oxidized silicon dioxide surface Si-H bonding into Si-OH which reacted with Hexamethyldisilazane (HMDS), commonly used as lithography adhesion material, and form an extremely thin Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on gate oxide surface. Fortunately, Trimethylsiloxy monolayer consists of Si-O bonding and Trimethylsilyl group (-Si(CH3)3) and can be easily removed by O2 plasma treatment. To reduce thermal budget, induced from furnace process of gate oxide formation, in triple gate oxide process, I/O gate oxide was obtained by thicker MV gate oxide wet chemical etching back, showed as Figure 1. However, when I/O gate oxide was removed at LV area, showed as Figure 1, step 6, wet etching rate was decreased. Reviewing similar process in I/O area wet etching back process, showed as Figure 1, step 4, the wet etching rate was normal. To figure out why wet etching rate is different between step 4 and step 6 in Figure 1, both 1:200 dilute HF and gas type HF etching rate and etching rate variation percentage with as growth data were collected by blanket silicon dioxide (SiO2) wafer which quality is same as MV gate oxide and result is showed as Table I. Clean is Piranha and SC1, including SPM (sulfuric acid and hydrogen peroxide mixture, H2SO4+ H2O2) and APM (ammonia, hydrogen peroxide and deionized water mixture, NH3+ H2O2+ H2O) process steps. In Table I, 1:200 dilute HF etching rates are normal after clean and after HMDS treatment, respectively. However, once combining clean and HMDS treatment, 1:200 dilute HF etching rate was decreased around 7.2%, but gas type HF etching rate didn’t show the same phenomena. Moreover, additional O2 plasma treatment was added in final step, 1:200 dilute HF etching rate became normal. HMDS is commonly used adhesives between photo resist and coating surface. The mechanism is silylation reaction, showed as Figure 2. HMDS reacted with SiO2 surface hydroxyl group (-OH) and formed Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on SiO2 surface which changing surface property from hydrophilic into hydrophobic. Adhesion between Photo resist and SiO2 surface had been improvement due to the enhancement of van der Waals’ force. Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation amount depends on hydroxyl group (-OH) amount on SiO2 surface. From Table II, after clean process, SiO2 surface hydroxyl group (-OH) increase due to the existence of hydrogen peroxide in clean chemical. The SiO2 surface become more hydrophilic, water contact angle decreased from 35.3° to 14.8°. After HMDS priming, SiO2 surface hydroxyl group (-OH) were substituted by Trimethylsiloxy group (-O-Si(CH3)3). The SiO2 surface become hydrophobic, water contact angle increased from 35.3° to 52.2°. After combining clean and HMDS processes, the water contact still increased from 52.2° to 59.1°. It means after clean process, some Si-H bondings oxidized by hydroperoxide into hydroxyl group (-OH), which will increase final Trimethylsiloxy monolayer (Si-O-Si(CH3)3) amount on SiO2 surface. After O2 plasma process, SiO2 surface was back to as growth condition by compatible water contact angle result. Reviewing Table I data, 1:200 dilute HF etching rate dropped main root cause is the existence of Trimethylsiloxy monolayer (Si-O-Si(CH3)3). The densification of this monolayer might be not as good as from deposition process and results in gas type HF can easily penetrate to bottom oxide layer and no etching rate was impacted. Fortunately, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be removed by O2 plasma treatment. To replace one of triple gate oxide growth under high temperature by thicker gate oxide wet etching back process. Post etched clean step and HMDS in following step will interfere with dilute HF etching behavior due to Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation. By adding additional O2 plasma treatment, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be easily and successfully removed and wet dilute HF SiO2 etching rate was back to normal. The thermal budget of triple gate oxide process can be successfully reduced by gate oxide wet etching back technique. Figure 1

We present a novel approach for the fabrication of single pore microcavities in silicon (111) based on Silicon-on-Insulator substrates and a combination of optical and electron-beam lithography, reactive ion etching and anisotropic wet etching techniques. Using a dedicated sequence of physical vapor deposition, electroplating and surface chemical oxidation, a silver/silver chloride (Ag/AgCl) reference bottom electrode was integrated into the cavity. We have fabricated cavities of volume ∼180 fl terminated at their top with silicon-nitride membranes featuring a single access pore of diameter 150–500 nm, each. Scanning electron microscopy revealed the cavity structure to comprise a hexagonal geometry top silicon nitride membrane and a triangular bottom plane. Atomic force microscopy analysis was performed on the AgCl surface, showing a root-mean-square surface roughness of 43.5 nm, hence resulting in a favorable high surface area of the electrode. We fully characterized our cavities filled with potassium chloride electrolyte solutions in electrical measurements to verify functionality of the integrated reference electrodes. Measured ion currents were stable over 1 d and scaled properly with pore diameter and salt concentration. We suggest our device to serve as platform for the controlled investigation of (bio-) electrochemical processes in smallest confined volumes.

Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.

Patterning of silicon is necessary in a number of microelectronic and micromechanic applications. Plasma processes, such as reactive ion etching, play an important role in VLSI and nanotechnology applications. The charged particles impinging onto the semiconductor surface may cause radiation damage, such as crystal defects of different dimensionality. In plasma etching processes resist patterning and a large number of processing steps are needed to perform etching. The laser-induced dry etching (LDE) process offers the possibilities of direct pattern transfer by mask projection, anisotropic etching with negligible damage, and etching with very high selectivity. Modifying the LDE-process by applying a microwave-excited gas results in more radicals and an increased etch rate. Some authors use Cl2 as the processing gas during the microwave-assisted laser dry etching (MALDE) with excimer laser radiation (248 nm) [1,2]. In this case the etch rate of Si(100) is below 1 A/pulse.

The conventional large radii bends used in large cross section silicon-on-insulator waveguides were replaced with novel wet etched corner mirrors, potentially allowing much smaller devices, therefore lower costs. If such corners had been based on reactive ion etch techniques they would have had the disadvantage of rougher surfaces and poor alignment in the vertical direction. Wet etching overcomes these two problems by providing smooth corner facets aligned precisely to the vertical {100} silicon crystallographic planes. The waveguides obtained had angled walls, and so numerical analysis was undertaken to establish the single mode condition for such trapezoidal structures. To show the relationship between fabrication tolerances and optical losses a three dimensional simulation tool was developed, based on expansion of the incident mode into plane waves. Various new fabrication techniques were are proposed, namely: the use of titanium as a mask for deep silicon wet anisotropic etching, a technique for aligning masks to the crystal plane on silicon-oninsulator wafers, a corner compensation method for sloping sidewalls, and the suppression of residues and pyramids with the use of acetic acid for KOH etching. Also, it was shown that isopropyl alcohol may be used in KOH etching of vertical walls if the concentration and temperature are sufficiently high. As the proposed corner mirrors were convex structures the problem of undercutting by high order crystal planes arose. This was uniquely overcome by the addition of some structures to effectively convert the convex structures into concave ones. The corner mirrors had higher optical losses than were originally hoped for, similar to those of mirrors in thin film waveguides made by RIE. The losses were possibly due to poor angular precision of the lithography process. The design also failed to provide adequate mechanisms to allow the etch to be stopped at the optimal time. The waveguides had the advantage over thin film technology of large, fibre-compatible cross sections. However the mirror losses must be reduced for the technology to compete with existing large cross section waveguides using large bends. Potential applications of the technology are also discussed. The geometry of the crystal planes places fundamental limits on the proximity of any two waveguides. This causes some increase in the length of MMI couplers used for channel splitting. The problem could possibly be overcome by integrating one of the mirrors into the end of the MMI coupler to form an L shaped junction.

To make three dimensional micron structures, the directional deep etching techniques are very important. The directional wet etching technique is often used for the bulk micromachining. However, directions of the wet deep etching and profiles of products are restricted by the crystalline orientation of silicon substrate. To solve this problem, high speed and deep directional dry etching processes have been studied. The low temperature reactive ion etching (RIE) apparatus for the bulk micromachining was fabricated and the etching characteristics were investigated. The high etch rate of 0.022 /spl mu/m/s and the low normalized side etch ratio of 0.021 were realized at the cathode temperature of -80/spl deg/C. The etch rate is equal or a little higher than that of the directional wet etching.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparative study on dry etching of polycrystalline diamond thin films

The group-III nitrides have become versatile semiconductors for short wavelength emitters, high temperature microwave transistors, photodetectors, and field emission tips. The processing of these materials is significant due to the unusually high bond energies that they possess. The dry and wet etching methods developed for these materials over the last few years are reviewed. High etch rates and highly anisotropic profiles obtained by inductively-coupled-plasma reactive ion etching are presented. Photoenhanced wet etching provides an alternative path to obtaining high etch rates without ion-induced damage. This method is shown to be suitable for device fabrication as well as for the estimation of dislocation densities in n-GaN. This has the potential of developing into a method for rapid evaluation of materials.

The technique of the anisotropic wet chemical etching had turned into one of the widely used processes for manufacturing the functional materials in microelectromechanical systems. To better understand the issues of growth mechanisms for the characteristic surface morphologies during an anisotropic chemical etching, in this study the formation and evolution of surface structures were investigated by numerical simulation methods. A chemical etching model was established on the basis of chemical reaction and atomic diffusion. Affecting by the anisotropy of the crystalline structure and etching rate, various featured surface morphologies, including the rippling surface, cusp-like hillock, and nano-pyramid, were numerically developed in accordance with the etching conditions. These characteristic structures were also in well agreements with the corresponding experiments. From the theoretical point of view, the surface morphologies were critically influenced by the kinetic factors of the anisotropic etching rate and the atomic diffusion. With the enhancement of theoretical work in the formation mechanism for the anisotropic chemical etching, the practical technique would possess a more competitive advantage for the wide applications in the fields of the functional materials fabrication.

Even with the copious advances in logic device fabrication, integration of new channel materials would represent a significant advance in CMOS technology. [1] Successful integration of new channel materials (III-V’s, Ge and SiGe) pose significant challenges for etch technology. Dry (plasma) etch technology can be used to pattern channel materials after they are deposited using an epitaxial process [2]; alternatively channels maybe inserted into bounded (for example an oxide) recesses (for example silicon) fabricated using etch technologies already developed for FinFET and SAQP applications. Less appealing is the use of wet processes that have troublesome crystallographic orientation dependencies. Dry etch technology for most new channel material candidates is not new. [3] Still, with dry etch technology there is the ever-present worry of damage. [4-6] High precision etch technology commonly referred to as atomic later etching (ALE) is an emerging viable option for new channel material integration. [7-10] Some approaches employ non-mainstream techniques such as neutral beam technology [8] or complex precursors. [10] Recent developments reinforce that conventional plasma etch technologies developed using concurrent engineering methods can meet the requirements for 7 and 5 nm logic fabrication. [7,11] This presentation will show how advanced plasma etch technologies provide a path for logic manufacture beyond 7 nm with a realistic picture of the trade-offs that must be handled for the introduction of III-Vs, Ge or SiGe. All in all, etch technologies if successfully implemented for new channel material integration relies of leveraging surface chemistry mechanisms. The presentation will be rounded out with a discussion of how first-principles methods (e.g., DFT methods) can be used to gain insight into important plasma –surface interaction mechanisms. S. Takagi et al., Japanese Journal of Applied Physics 54, 06FA01 (2015) Chen et al,. Nanoscale Research Letters, 7, 431 (2012) Plasma Etching of III–V Nitrides,” by R. Shul, in Processing of Wide Band Gap Semiconductors: Growth, Processing and Applications, 250 (2000), ed., S.J. Pearton F.D. Auret et al., Physica B, 407, 1497 (2012) Kasumandari et al., Appl. Phys. Lett., 103, 033511 (2013) “Dry Etching of Semiconductors at the Nano-and Micro-Scale” by S.J. Pearton in Vistas in Nanofabrication, (2012) A. Ranjan et al., J. Vac. Sci. Technol. A 34, 031304 (2016) S.D. Park et al., Appl. Phys. Lett. 91, 013110 (2007); C. T. Carver et al., ECS J. Sol. St. Sci. Tech., 4 N5005-N5009 (2015) S. M. George, Chem. Rev., 110, 111 (2010) S.D. Sherpa et al., J. Vac. Sci. Technol. A 35, 01A102 (2017)