Dry and Wet Etching for Group III – Nitrides

Up until the late 1960s, chemical etching, also called wet solvent etching, was the key technology to integrated circuit manufacturing. Indeed, from the standpoint of manufacturing, wet etching provides low cost and often infinite selectivity. But, inherent limitations in wet etching preclude the use of this technique for micron and submicron pattern sizes. The most serious limitation is that of isotropic etching, which results in undercutting of the mask material and hence limits the minimum size of the pattern. To obtain high-density packing of microelectronic circuits, anisotropic etching is essential. By the early 1970s, CF /02 dry etching was widely adopted for patterning. It was widely recognized that dry etching offered the possibility of a vertical etch rate that greatly exceeded the horizontal etch rate (namely anisotropic etching). As a result, these dry etching techniques, which can generate anisotropic etch profiles, came into prominence. Dry etching soon began to appear in IC fabrication. However, these dry etching technologies, like wet processes, had their resolution limited by undercutting, and other, even more anisotropic etching techniques appeared. Among these were reactive ion etching (RIE). The RIE technique which has been widely adopted for IC fabrication until now provides moderate selectivity, etch rate and high anisotropy. In the mid-to-late 1970s, research began on a dry etch technique which would combine the positive features of RIE with directional bombardment of the surface by ions accelerated through electrostatic sheaths. Figure 1.1 shows how integrated circuits have evolved and how the number of individual components per circuit has increased with time. It is seen in the figure that the component density of IC circuits has doubled every year and this yearly doubling rate has been maintained from the first IC in 1960 until recently. At the same time, the design feature size has shrunk from 6 μm to 0.8 μm in the last 15 years, and the smallest dimensions are expected to decrease to 0.1 μmin the near future.

Background: CR-39 nuclear track detectors are widely used in various fields, including science, technology, astronomy, and environmental preservation, to detect and register heavy ions, neutrons, and alpha particles. Objective: This study aims to determine the optimal etching duration for CR-39 nuclear track detectors by comparing etching methods: The wet etching (using a water bath) and the dry etching technique (using dielectric barrier discharge (DBD) plasma). Methods: The traditional etching method involved immersing CR-39 detectors in a sodium hydroxide (NaOH) solution at 70 °C for varying durations. The dry etching method employed employs a non-thermal DBD plasma system to etch solid-state nuclear track detectors (SSNTDs) without the use of chemical solutions. Results: Photomicrographs revealed that tracks from chemical etching became clearly visible after 1 hour and developed at 5 hours. In contrast, the dry etching technique was significantly faster; tracks began to appear after just 1 minute of DBD plasma etching and were fully developed at 5 minutes. The optimum track density for DBD plasma was 20340±56 tracks/mm2 at 3 minutes, whereas the traditional water bath method achieved an optimum track density of 5238.0±5.7 tracks/mm2 at 2 hours. The shorter etching duration in the dry method likely facilitates the emergence of latent tracks without overlap. Conclusions: The bulk etch rate (VB) for CR-39 detectors using the dry DBD plasma etching technique was faster compared to the traditional chemical etching method. This demonstrates the efficacy of the dry etching process in significantly reducing etching time required for etching SSNDs.

The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely the wet chemical etching method, using HNO3-HF-CH3COOH solution, and the Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching using inert gas only (e.g., argon gas), and ion chemical etching using an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning microscope (OSM) and Joel Scanning microscope (JSM). The formed hole width (ω) increases by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about ( 0.0707 and 0.0537 µm/min ) .Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. Normal 0 21 false false false MS X-NONE X-NONE The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely wet chemical etching method, using HNO3-HF-CH3COOH solution, and Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching used inert gas only (e.g., argon gas) while ion chemical etching used an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning Microscope (OSM) and Joel Scanning Microscope (JSM). The formed hole width (ω) increased by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about (0.0707 and 0.0537 µm/ min). Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

Dry etching or plasma-assisted etching (ion beam milling, plasma etching and reactive sputter etching) has become an indispensable preparation technique for high resolution pattern transfer in IC manufacturing and other areas of microfabrication. Etching can either be due to the purely physical process of momentum transfer from ions to the solid surface (e.g. inert ion etching) or due to chemical reactions of reactive species, produced in the plasma, with the solid surface resulting in a volatile reaction product (e.g. plasma etching in a barrel reactor). However, in most dry etching methods both effects play a major role and it is possible to optimize etch selectivity and the shape of the etched profile by a proper choice of parameters.

With ever-decreasing feature size in devices along with increasing wafer diameter, single wafer plasma etchers have drawn much attention recently, because of uniform and reproducible etching as well as improved process control. High etch rate with good selectivity is necessary in order to economically compete with batch machines. In response to this requirement, a reactive ion etch process is developed that, by employing hydrogen bromide, provides both high polysilicon etch rate and high selectivity to gate oxide at the same time in an anisotropic etching of P-doped polysilicon. Furthermore, photoresist erosion rate is very low in the brominated plasma; there is virtually no linewidth loss in the processing even when the photoresist profile is substantially sloped. Silicon trench etching has also been achieved at high rate with HE3r-based plasma. The deep silicon trench with high aspect-ratio shows smooth etched surface, rounded bottom corner, and a slightly positive slope profile.

Reactive Ion Beam Etching (RIBE) has been found to be an extremely useful technique for fabricating highly anisotropic ferroelectric device structures, particularly nonvolatile random access (NVRAM) memory devices, which are difficult to etch by other dry etching methods. The application of ion beam equipment to this field has been limited in the past by the use of standard Kaufman type ion sources, which have very short cathode lifetimes when operated with the reactive gases which are used to attain enhanced selectivity. This problem is solved by using the RF inductively coupled ion source described here. Etch results on ferroelectric PZT and Pt electrodes are presented for the RF source and compared with results for a Kaufman filament ion source. It is shown that RF RIBE with fluorocarbon gases provides higher etch selectivity for the ferroelectric (up to about 4:1 PZT/Pt) combined with relatively high etch rates (650 A/min for PZT at 500 eV). A complete practical ion beam process for patterning ferroelectric device structures is then described, incorporating the ferroelectric RIBE step. Highly anisotropic etched features are shown.

Silicon (Si) etching process with low temperature is used for initial processing of semiconductor field emitter array cathodes for vacuum microelectronics, for optical reflecting gratings, for opto- and micromechanical devices. Most of them are performed by dry etching process especially in reactive ion etching (RIE) method with fluorocarbon-gases such as CF4, CHF3 and C3F8. In this work, results are shown that reactive ion etching of silicon using CF4/H2 is capable at meeting the requirement (anisotropy, high etch rate and high selectivity, simultaneously) similar to that by using reactive ion etching with fluorine-containing plasma. We have investigated the etching rate dependency on the percentage of hydrogen in the gas mixture, the total pressure and flow gas and found that by using a gas mixture with 33% of H2, the optimum rate of Si is achieved. The etch rate are found to increase with voltage, attaining a maximum rate 1780 Å/min at -482V. Surface morphology of the etched samples is characterized by scanning electron microscopy and atomic force microscopy. The results revealed that the etched surface was anisotropic and the smoothness of the etched surface is comparable to that of polished wafer.

We investigate the ridge-width dependence of the threshold of Quantum Cascade lasers fabricated by wet and dry etching, respectively. The sloped sidewalls resulting from wet etching affect the threshold in two ways as the ridge gets narrower. First, the transverse modes are deeper in the substrate, hence reducing the optical confinement factor. Second, more important, a non-negligible field exists in the lossy SiO2 insulation layer, as a result of transverse magnetic mode coupling to the surface plamon mode at the insulator/metal surface, which increases the waveguide loss. By contrast, dry etching is anisotropic and leads to waveguides with vertical sidewalls, which avoids the shift of the modes to the substrate layer and coupling to the surface plasmons, resulting in improved threshold compared with wet-etched lasers, e.g., for narrow ridge widths below 20 µm, the threshold of a 14 µm wide λ ≈ 14 µm laser by dry etching is ~60% lower than that of a wet-etched laser of the same width, at 80 K.

Approaches for patterning of aluminum

Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.

To make three dimensional micron structures, the directional deep etching techniques are very important. The directional wet etching technique is often used for the bulk micromachining. However, directions of the wet deep etching and profiles of products are restricted by the crystalline orientation of silicon substrate. To solve this problem, high speed and deep directional dry etching processes have been studied. The low temperature reactive ion etching (RIE) apparatus for the bulk micromachining was fabricated and the etching characteristics were investigated. The high etch rate of 0.022 /spl mu/m/s and the low normalized side etch ratio of 0.021 were realized at the cathode temperature of -80/spl deg/C. The etch rate is equal or a little higher than that of the directional wet etching.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Surface damage in Si substrates created by Ar-ion milling or by reactive-ion etching in CF4, CHF3, Cl2, SiCl4, or SiF4 has been investigated. Metal-oxide-semiconductor capacitors were fabricated on the etched Si substrates, and the interface-state densities were obtained from capacitance-voltage measurements. Interface states generated by the dry etching processes were strongly dependent on the etching gas and the bias voltage. Carbon-based gases (CF4, CHF3) induced more interface states than those without carbon. For the carbon-based gases, Si samples etched in CHF3 showed lower densities of interface states than samples etched in CF4 under the same conditions. Generation lifetime measurements indicated that samples with large densities of interface states also had short lifetimes. Measurements of oxidation-induced stacking faults caused by dry etching were consistent with both the interface-state and lifetime measurements. Thermal annealing of the etched wafers was not effective in reducing the surface damage. The measured interface states on the dry etched Si substrates could be lowered to their pre-etched levels by removing at least 500 Å of the etched surface by wet chemical etching.

Surface morphology and removal rates for dry- and wet-etched novel resonator materials: Part II. La 3Ga 5.5Nb 0.5O 14

Recently, the important issues relating to the photovoltaic cell have featured low cost and high efficiency. To make a low-cost and high-efficiency photovoltaic cell, there are many aspects such as the development of inexpensive wafers, process simplification and improvement of optical and electrical properties. In this study, the two-step texturing method using a microblaster was developed to decrease the reflection of incident lights. Bridge-type electrode structures are suggested to expand the effective surface area and decrease the series resistance of finger electrodes. The authors decided to use 10 µm size powders since the efficiency of the solar cell could rather be reduced by using 50 µm size powders because of their extremely rough surface. And the surface of the wafer after microblaster etching was treated with a chemical etching method using HNA (HF:HNO3:CH3COOH=4:9:7) solution, a dry etching method using reactive ion etching and a oxide etching method.

A high performance silicon dry etch process (STS Advanced Silicon Etch ASE) which in many cases is a beneficial replacement for the usual anisotropic wet etch methods like KOH etching is presented. During fabrication of Micro-Electro- Mechanical Systems (MEMS) the patterning of silicon is an essential step. Conventional wet or dry etching processes used up to now cannot meet the majority of future MEMS patterning needs. The process described in this paper allows a wide range of possible geometries and freedom of design and mask layout for novel MEMS applications. The installed etch system is working with an inductively coupled plasma source (ICP) which produces high plasma densities at low pressure to achieve deep silicon etching (greater than 200 micrometer) with high etch rates up to 5 micrometer/min and a high passivation layer selectivity. The new ASE process uses only fluorine based chemistry and operates at room temperature. ASE uses photoresists and silicon oxid layers as an etch passivation and allows the manufacturing of silicon structures with nearly vertical side walls in bulk and surface micromachining illustrated by several MEMS applications carried out at the Fraunhofer Institute for Solid State Technology. With depths up to 100 micrometer realized at the institute now and an excellent anisotropic profile control ASE is obviously the tool, useful from device development to volume production of microsystems.