Dry etching for pattern transfer

Focused ion beams (FIB) have been widely used as a patterning lithography technique for advanced ICs and optical masks fabrication. FIB lithography has certain advantages over the direct-write electron beam lithography in terms of resist sensitivity, backscattering and proximity effects. However, combining the FIB exposure with both Top Surface Imaging (TSI) and dry etching will further extend its advantages towards anisotropic processing of thicker resist layers in comparison to those used by the conventional lithography processes. The newly developed NERIME (Negative Resist Image by Dry Etching) process combines these advantages by the incorporation of focused Ga+ ion beam (Ga+ FIB) exposure, near UV exposure, silylation and dry etching. The work described here follows our investigations into the NERIME process for nanostructure applications and outlines a simplified (two-step) process incorporating FIB exposure and oxygen dry development. The two-step modified NERIME process is a negative working TSI system for DNQ/novolak based resists. Results show that Ga+ ion beam dose higher than 800μC/cm2 at 30keV can modify the exposed resist areas as to withstand the subsequent oxygen plasma etching, thus giving formation of negative resist image. In this study, nanometer resist patterns as small as 30nm with high aspect ratio of up to 15 were successfully resolved due to the high resolution ion beam exposure and anisotropic dry development. The proposed two-step lithography scheme could be utilized for the fabrication of critical CMOS process steps, such as sub-100nm gate formations and lithography over substantial topography.

Even with the copious advances in logic device fabrication, integration of new channel materials would represent a significant advance in CMOS technology. [1] Successful integration of new channel materials (III-V’s, Ge and SiGe) pose significant challenges for etch technology. Dry (plasma) etch technology can be used to pattern channel materials after they are deposited using an epitaxial process [2]; alternatively channels maybe inserted into bounded (for example an oxide) recesses (for example silicon) fabricated using etch technologies already developed for FinFET and SAQP applications. Less appealing is the use of wet processes that have troublesome crystallographic orientation dependencies. Dry etch technology for most new channel material candidates is not new. [3] Still, with dry etch technology there is the ever-present worry of damage. [4-6] High precision etch technology commonly referred to as atomic later etching (ALE) is an emerging viable option for new channel material integration. [7-10] Some approaches employ non-mainstream techniques such as neutral beam technology [8] or complex precursors. [10] Recent developments reinforce that conventional plasma etch technologies developed using concurrent engineering methods can meet the requirements for 7 and 5 nm logic fabrication. [7,11] This presentation will show how advanced plasma etch technologies provide a path for logic manufacture beyond 7 nm with a realistic picture of the trade-offs that must be handled for the introduction of III-Vs, Ge or SiGe. All in all, etch technologies if successfully implemented for new channel material integration relies of leveraging surface chemistry mechanisms. The presentation will be rounded out with a discussion of how first-principles methods (e.g., DFT methods) can be used to gain insight into important plasma –surface interaction mechanisms. S. Takagi et al., Japanese Journal of Applied Physics 54, 06FA01 (2015) Chen et al,. Nanoscale Research Letters, 7, 431 (2012) Plasma Etching of III–V Nitrides,” by R. Shul, in Processing of Wide Band Gap Semiconductors: Growth, Processing and Applications, 250 (2000), ed., S.J. Pearton F.D. Auret et al., Physica B, 407, 1497 (2012) Kasumandari et al., Appl. Phys. Lett., 103, 033511 (2013) “Dry Etching of Semiconductors at the Nano-and Micro-Scale” by S.J. Pearton in Vistas in Nanofabrication, (2012) A. Ranjan et al., J. Vac. Sci. Technol. A 34, 031304 (2016) S.D. Park et al., Appl. Phys. Lett. 91, 013110 (2007); C. T. Carver et al., ECS J. Sol. St. Sci. Tech., 4 N5005-N5009 (2015) S. M. George, Chem. Rev., 110, 111 (2010) S.D. Sherpa et al., J. Vac. Sci. Technol. A 35, 01A102 (2017)

Background: CR-39 nuclear track detectors are widely used in various fields, including science, technology, astronomy, and environmental preservation, to detect and register heavy ions, neutrons, and alpha particles. Objective: This study aims to determine the optimal etching duration for CR-39 nuclear track detectors by comparing etching methods: The wet etching (using a water bath) and the dry etching technique (using dielectric barrier discharge (DBD) plasma). Methods: The traditional etching method involved immersing CR-39 detectors in a sodium hydroxide (NaOH) solution at 70 °C for varying durations. The dry etching method employed employs a non-thermal DBD plasma system to etch solid-state nuclear track detectors (SSNTDs) without the use of chemical solutions. Results: Photomicrographs revealed that tracks from chemical etching became clearly visible after 1 hour and developed at 5 hours. In contrast, the dry etching technique was significantly faster; tracks began to appear after just 1 minute of DBD plasma etching and were fully developed at 5 minutes. The optimum track density for DBD plasma was 20340±56 tracks/mm2 at 3 minutes, whereas the traditional water bath method achieved an optimum track density of 5238.0±5.7 tracks/mm2 at 2 hours. The shorter etching duration in the dry method likely facilitates the emergence of latent tracks without overlap. Conclusions: The bulk etch rate (VB) for CR-39 detectors using the dry DBD plasma etching technique was faster compared to the traditional chemical etching method. This demonstrates the efficacy of the dry etching process in significantly reducing etching time required for etching SSNDs.

This thesis describes the development of a dry plasma etch smoothing technique to replace the conventional Chemical Mechanical Polishing process within a device manufacturing scheme in the semiconductor industry. An important semiconductor manufacturing process is 3D wafer packaging, which allows vertical stacking of wafer die. 3D wafer packing represents a significant component of the total wafer level processing cost. A critical step in the 3D packaging process flow is the Chemical Mechanical Polishing process. Replacement of the CMP process step with a corresponding dry etch can yield significant time and cost savings. This is achievable through reductions in metrology and wafer handling requirements and lower volumes of materials needed for plasma-etch based processes compared with CMP. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200 nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6 nm is demonstrated, which is comparable to a virgin silicon wafer. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where these surface scratches are falsely identified as defects. The quality of the plasma polished surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification process followed by a roughness reduction iteratively, to produce a smooth surface without visible grind marks. Further work describes the application of the smoothing process to microneedles, with the aim of improving the process flow. Smoothing of silicon carbide has been performed. Finally, an extension of the TSV reveal process is described, called extreme thinning, with the development of a predictive model to minimize final total thickness variation. Silicon smoothing can also be beneficial to this application.

Direct write patterning of titanium films using focused ion beam implantation and plasma etching

There is a need to develop an etching technology for the fabrication of nanostructures which provides accurate etch rate control at the atomic level, mask pattern transfer at the nanometer scale, and a clean damage-free surface. In addition, it is highly desirable to integrate the etch with the growth so that in regrowth the problem of contamination is eliminated. Chemical beam etching inside a chemical beam growth system has a great potential of becoming such a dry etching technology. Etching at a subnanometer scale is conveniently monitored by using in situ reflection high energy electron diffraction. Unlike other dry etching methods, the only etching parameter that is critical for etch rate control is the gas flow rate. The etch rate varies linearly with the gas flow rate, which can be adjusted easily by well established mass flow technology. However, a surface roughening mechanism due to inadequate cation diffusion may change the initially two-dimensional (2D) process into a three dimensional (3D) etching. The effectiveness in surface impurity removal by etch cleaning also depends on the etched morphology. Using novel methods that enhance the surface cation diffusion, etching can be maintained in a 2D fashion to obtain a mirrorlike surface.

An effective mesa-isolation process using Cl-based gas chemistry and oxygen plasma post-treatment is investigated to minimize the effect of plasma-induced damage on AlGaN/GaN high-electron mobility transistor (HEMT) performance. Plasma-induced dc bias of the dry etching of AlGaN/GaN heterostructures is optimized using Cl2/BCl3/Ar gases by monitoring leakage current between adjacent mesas and etch profiles near mesa edges. A dc bias of ∼100 V leads to a smoother etched surface and mesa surface near mesa edge and a lower leakage current than dc bias of 260 V. AlGaN/GaN HEMTs fabricated under a dc bias of 100 V show a reasonable pinch-off performance but still high drain leakage current level (tens of microamperes). Oxygen plasma treatment after dry etching is introduced for further reduction in the leakage current. In situ oxygen plasma treatment more effectively improves the leakage current/breakdown performance than ex situ oxygen plasma treatment after the HEMTs are exposed to air. Combination of low-bias Cl-based dry etching and in situ plasma treatment leads to a breakdown voltage higher than 90 V and a drain leakage current of a few nanoamperes at (VDS,VGS)=(5 V,<VT). It is suggested that in situ oxygen treatment, together with low-bias dry etching, passivates the plasma-induced surface damage and results in good pinch-off/breakdown characteristics in AlGaN/GaN HEMTs.

The effect of powder particle size on the corrosion behavior of atmospheric plasma spray-Y2O3 coating: Unraveling the corrosion mechanism by fluorine-based plasma

The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89mV/dec and ION =42μA per stack (10.5μA per sheet) at VOV =VDS =−0.5V are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H2 O2 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.

A fast and inexpensive scheme for etch rate prediction using flexible continuum models and Bayesian statistics is demonstrated. Bulk etch rates of MgO are predicted using a steady-state model with volume-averaged plasma parameters and classical Langmuir surface kinetics. Plasma particle and surface kinetics are modeled within a global plasma framework using single component Metropolis Hastings methods and limited data. The accuracy of these predictions is evaluated with synthetic and experimental etch rate data for magnesium oxide in an ICP-RIE system. This approach is compared and superior to factorial models generated from JMP, a software package frequently employed for recipe creation and optimization.

ABSTRACTA dry etch fabrication technology for high-speed AlInAs/InGaAs Heterojunction Bipolar Transistors (HBT's) utilizing low-damage Electron Cyclotron Resonance (ECR) CH4/H2/Ar plasma etching is detailed. The dry etch process uses triple self-alignment of the emitter and base metals and the base mesa, minimizing the base-collector capacitance (CBC). Devices with 2 × 4 μm2 emitters demonstrated current gains of 30–50 with ft and fmax values of ≥ 80 GHz and ≥100 GHz respectively. The structure employs a two-stage collector to achieve breakdown voltage (Vceo ) of 7V. The combination of processing and layer structure delivers truly scalable high yield AlInAs/InGaAs HBT's with both DC and RF characteristics suitable for large-scale, high speed digital circuit applications.

Metal–organic materials such as [NH2(CH2–CH=CH2)2][Cr7NiF8(Pivalate)16] can act as negativetone resistsfor electron beam lithography (EBL) with high-resolution patterningof sub-40 nanometer pitch while exhibiting ultrahigh dry etch selectivities>100:1 and giving line dose exposures >11,000 pC/cm. It is clearthatthe resist sensitivity is too low to be used to manufacture the latestnanoscale photomasks that are suitable for extreme ultraviolet lithography.Therefore, the focus of this work here is to improve the sensitivityof this resist while maintaining its resolution and dry etch selectivity.Using our latest Monte Carlo simulation called Excalibur, we predictthat the sensitivity would increase by a factor of 1.4 when the nickelatom is substituted by a cadmium atom. EBL studies showed an excellentagreement with the simulation, and plasma etching studies demonstratedthat this did not affect the dry etch performance of the resist whichremains very good with a selectively of ca. 99:1 for the etching ofsilicon at these resolutions with a low sensitivity of 7995 pC/cm.

Plasma etching of III–V semiconductor thin films

Atomic layer etching (ALE) is set to be a vital part of the advanced semiconductor manufacturing toolbox, known for its precise control of the film thickness and minimal damage. These benefits are possible due to the sequential self-limiting half-cycles that are employed within an ALE process. Initially, ALE was underestimated due to low etch rates, but it is now experiencing a renaissance due to the requirements imposed by further downscaling.1 The ALE community is mostly divided into two groups: plasma anisotropic and thermal isotropic etching. 2 In this work, the focus is on exploring isotropic plasma ALE, which is a relatively unexplored direction. This approach involves using plasma radicals to modify and/or etch material isotropically, while minimizing the directional ion component of the plasma. Isotropic plasma ALE can offer several benefits over strictly thermal ALE, such as higher etch rates, lower operating temperatures, and the ability to etch more resistant materials.In this talk we will first address some of the different techniques employed for plasma isotropic ALE in the literature. Subsequently, we will discuss our own work, which has focused on two isotropic plasma ALE chemistries. The first involves alternating between plasma fluorination and ligand-exchange half-cycles, this ALE chemistry has been found to be effective for etching Al2O3, HfO2, AlN, and GaN films.3,4 Surface contaminants and roughness were found to be reduced post ALE, an aspect that is particularly important for AlN and GaN films that are used in quantum, power semiconductor and LED applications. The second approach involves using diketone (e.g. acetylacetone, hexafluoroacetylacetone) doses followed by either H2 or O2 plasma exposures for ALE of Al2O3 and ZnO.5 The diketone in this process acts to etch the surface, however due to competitive adsorption of different diketone orientations an etch inhibition layer forms. The plasma step is then utilized to clean the surface, removing the self-limiting inhibitor layer, enabling etching to continue in the next cycle. This ALE chemistry diverges from the typical modification/removal ALE cycle, where a modified layer if often observed on the material post ALE. In comparison the diketone ALE chemistry does not rely on modification of the surface making it an ideal process for surface cleaning. This approach provides improved selectivity over the plasma fluorination process and also enables smoothing.Plasma isotropic ALE is a growing part of the ALE community that can help accelerate the adoption of ALE in academia and industry. The potential benefits of ALE are only just beginning to be explored, and more processes are needed to etch the ever-increasing range of materials utilized in IC manufacturing. Kanarik, K. J., Tan, S. & Gottscho, R. A. Atomic Layer Etching: Rethinking the Art of Etch. J Phys Chem Lett 9, 4814–4821 (2018).George, S. M. Mechanisms of Thermal Atomic Layer Etching. Acc Chem Res 53, 1151–1160 (2020).Chittock, N. J. et al. Isotropic plasma atomic layer etching of Al2O3 using a fluorine containing plasma and Al(CH3)3. Appl Phys Lett 117, 162107 (2020).Wang, H., Hossain, A., Catherall, D. & Minnich, A. J. Isotropic plasma-thermal atomic layer etching of aluminum nitride using SF6 plasma and Al(CH3)3. 1–14 (2022) doi:arXiv.2209.00150.Mameli, A., Verheijen, M. A., Mackus, A. J. M., Kessels, W. M. M. & Roozeboom, F. Isotropic Atomic Layer Etching of ZnO Using Acetylacetone and O2 Plasma. ACS Appl Mater Interfaces 10, 38588–38595 (2018).

Resists used in plasma processing