Resists used in plasma processing

Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (<200 °C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100% (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm2/V s) is not impacted by the etch process.

InGaN-based light emitting diodes (LEDs) were fabricated through a photoelectrochemical (PEC) wet mesa etching process to replace the conventional dry mesa etching process. The undercut structures were formed from a bandgap-selective lateral wet etching process that occurred at the InGaN/GaN multiple-quantum-well layers. By measuring the selective-area microphotoluminescence spectra focused on the mesa edge region, the blueshift wavelength of the photoluminescence spectrum in the wet mesa etched light emitting diode (WME-LED) was 9.1 nm (55 meV) that was compared to the conventional dry etching LED. The relative internal quantum efficiencies of WME-LED were calculated as 13.7% (at the first region), 21.8% (at the second region), and 24.5% (at the third region) from the mesa center to the edge. The flatband voltage of the WME-LED was −13 V to balance the piezoelectric field, calculated as −1.17 MV/cm, in the InGaN active layer. However, we did not observe any flatband voltage in the conventional LED up to −19 V (piezoelectric field larger than −1.9 MV/cm). By forming the bending undercut structure on p-type GaN:Mg layer, the lattice mismatch induces a compressed strain and a piezoelectric field in the InGaN active layer that can be partially released in the WME-LED by using a PEC wet mesa etching process.

The wet etching process in photomask fabrication could not meet requirements for small features for high density devices having optical proximity correction (OPC) features. Therefore, a dry etching process should be employed in mask making. However, there are some critical issues in dry etching process: one of the most important issues is critical dimension (CD) variation across the mask due to the loading effect during dry etching. CD errors caused by dry etch process are known to be originated from non-uniformity of plasma, non-vertical resist profile, and loading effect due to the various pattern densities. In case of loading effect, we are concerned about only macro-loading effect rather than micro-loading effect because the aspect ratio in the photomask is very small compared to that in the wafer. After dry etch, the patterns surrounded with large chrome area have large CDs because of the lower etch rate. We found that the macro-loading effect was about 5-10nm. And the effective range of the loading effect is amount to more than 10mm. In order to improve the CD variation caused from loading effect, we should optimize process conditions based on plasma uniformity, etch selectivity, resist profile, etc. However, it is a time consuming job. In this paper, we present a new method to improve loading effect, which is used for correcting e-beam proximity effect. Once we know the degree of loading effect, we can compensate it by allocating various doses at necessary locations.

The quantitative comparison of the electron mobility (u/sub eff/) in the poly-Si gated n-channel multi-FinFETs fabricated by the orientation-dependent wet etching and conventional RIB processes has been carried out. A remarkable increment in u/sub eff/ has experimentally been confirmed in the Si-fin channels fabricated by the wet etching instead of the RIB. Therefore, it is concluded that the developed wet etching technique is very attractive for the fabrication process of the high quality and ultra-thin Si-fin channel FinFETs.

The effect and influence of dry plasma etching processes of Si/SiGe using HBr for the formation of diode mesa structures has been investigated to minimise sidewall leakage current. To characterise sidewall damage electrically, Si-based resonant interband tunnel diodes (RITD) were processed and the completed RITDs compared by their peak-to-valley current ratio (PVCR) and valley current density (VCD), which are sensitive to defect related currents. Dry processed RITDs were compared to reference RITDs fabricated by wet chemical etching (HNO3:HF:H2O=100:1:100). The combination of HBr process gas and very low substrate bias power (10 W) for inductively coupled plasma reactive ion etching (ICP-RIE) yielded the better results. The resulting RITDs processed by ICP-RIE using HBr chemistry show high PVCR of 4.02 with VCD of 32 A/cm2 while wet etched RITDs show a PVCR of only 2.81 with VCD of 40 A/cm2. Hydrogen passivation during the HBr plasma process may play a role that overcomes the slightly higher surface roughness compared to wet etching.

Self-assembly block copolymers have drawn a lot of attention for its great potential on critical dimension (CD) control and line-edge roughness (LER) reduction, which become more and more crucial as the CD of transistors is only tens of nanometers nowadays. In this study, lamellar-forming poly(styrene-b-methyl methacrylate) copolymer which fabricates line patterns was chosen for its ability to provide higher aspect ratio and vertical sidewall profile in template stage, thus more suitable for the following etching process to substrate. A dry plasma etching process using pure oxygen and pure argon plasma as example chemical etching gas and physical etching gas, respectively, was studied. Etching selectivity and lateral etch rate, which are responsible for the final template height and CD loss, had been characterized on a capacitive reactive ion etching tool. The templates formed by the proposed process had high aspect ratios, excellent pattern fidelity, and low LER values. The PS lateral etch rate was small enough to provide a wide process window for retaining the CD of the pattern during the template forming process. Subsequent silicon etching using the PS template made by dry etching process yielded a steep and smooth sidewall profile.

The incorporation of dry etch processes for mercury cadmium telluride (HgCdTe) infrared device fabrication is becoming critical for the infrared community as we advance toward the production of high-density devices. Dry etch processes are cleaner than wet etch processes. In addition, dry etches are highly anisotropic and are capable of producing the small features required by the more advanced device architectures. However, the incorporation of dry etch processes into device fabrication often affects the surface quality, producing roughened surfaces and variations in composition. Consequently, the identification of suitable dry etch processes to produce high quality infrared devices is essential. In this investigation, three different plasma etching tools (reactive ion etching, electron cyclotron resonance, and remote microwave) were used to etch HgCdTe with hydrogen. The hydrogen interaction with HgCdTe at similar etch depths was examined with spectroscopic ellipsometry and atomic force microscopy. Variations in surface roughness and composition obtained when etching with the three plasma etching tools are reported and the significance of energetic ions on surface quality is discussed.

With the inherent advantages of good Critical Dimension (CD) control and good pattern fidelity, dry etching of Chrome-on- Quartz (COG) binary masks is necessary for production of 0.18um or below technology generation masks. Chrome dry etching process, however, tends to produce more defects than the traditional wet etch processes. We have conducted in-process defect inspection studies, which have identified several defect sources and have proposed process controls that minimize the number and size of defects from the entire dry etch process. This paper discusses the design of a defect test vehicle and describes an approach and methodology of defect inspection as a means of understanding the creation mechanisms of process related defects. A Lasertec Corporation (i)-line inspection system is employed along with different microscopy and metrology tools to identify and characterize these defects that can be attributed to the various steps in this entire dry etch process. Our results demonstrate that this approach of in-process inspection is very effective at identifying defects and their sources as they become evident at different process steps.

Background: CR-39 nuclear track detectors are widely used in various fields, including science, technology, astronomy, and environmental preservation, to detect and register heavy ions, neutrons, and alpha particles. Objective: This study aims to determine the optimal etching duration for CR-39 nuclear track detectors by comparing etching methods: The wet etching (using a water bath) and the dry etching technique (using dielectric barrier discharge (DBD) plasma). Methods: The traditional etching method involved immersing CR-39 detectors in a sodium hydroxide (NaOH) solution at 70 °C for varying durations. The dry etching method employed employs a non-thermal DBD plasma system to etch solid-state nuclear track detectors (SSNTDs) without the use of chemical solutions. Results: Photomicrographs revealed that tracks from chemical etching became clearly visible after 1 hour and developed at 5 hours. In contrast, the dry etching technique was significantly faster; tracks began to appear after just 1 minute of DBD plasma etching and were fully developed at 5 minutes. The optimum track density for DBD plasma was 20340±56 tracks/mm2 at 3 minutes, whereas the traditional water bath method achieved an optimum track density of 5238.0±5.7 tracks/mm2 at 2 hours. The shorter etching duration in the dry method likely facilitates the emergence of latent tracks without overlap. Conclusions: The bulk etch rate (VB) for CR-39 detectors using the dry DBD plasma etching technique was faster compared to the traditional chemical etching method. This demonstrates the efficacy of the dry etching process in significantly reducing etching time required for etching SSNDs.

The main objective of this work is to demonstrate and validate the feasibility of fabricating (Al, In) GaN laser diodes with etched facets. The facets are fabricated using a two-step dry and wet etching process: inductively coupled plasma—reactive ion etching in chlorine, followed by wet etching in tetramethylammonium hydroxide (TMAH). For the dry etching stage, an optimized procedure was used. For the wet etching step, the TMAH temperature was set to a constant value of 80 °C, and the only variable parameter was time. The time was divided into individual steps, each of 20 min. To validate the results, electro-optical parameters were measured after each step and compared with a cleaved reference, as well as with scanning electron microscope imaging of the front surface. It was determined that the optimal wet etching time was 40 min. For this time, the laser tested achieved a fully comparable threshold current (within 10%) with the cleaved reference. The described technology is an important step for the future manufacturing of photonic integrated circuits with laser diodes integrated on a chip and for ultra-short-cavity lasers.

Surface damage in Si substrates created by Ar-ion milling or by reactive-ion etching in CF4, CHF3, Cl2, SiCl4, or SiF4 has been investigated. Metal-oxide-semiconductor capacitors were fabricated on the etched Si substrates, and the interface-state densities were obtained from capacitance-voltage measurements. Interface states generated by the dry etching processes were strongly dependent on the etching gas and the bias voltage. Carbon-based gases (CF4, CHF3) induced more interface states than those without carbon. For the carbon-based gases, Si samples etched in CHF3 showed lower densities of interface states than samples etched in CF4 under the same conditions. Generation lifetime measurements indicated that samples with large densities of interface states also had short lifetimes. Measurements of oxidation-induced stacking faults caused by dry etching were consistent with both the interface-state and lifetime measurements. Thermal annealing of the etched wafers was not effective in reducing the surface damage. The measured interface states on the dry etched Si substrates could be lowered to their pre-etched levels by removing at least 500 Å of the etched surface by wet chemical etching.

Patterning of silicon is necessary in a number of microelectronic and micromechanic applications. Plasma processes, such as reactive ion etching, play an important role in VLSI and nanotechnology applications. The charged particles impinging onto the semiconductor surface may cause radiation damage, such as crystal defects of different dimensionality. In plasma etching processes resist patterning and a large number of processing steps are needed to perform etching. The laser-induced dry etching (LDE) process offers the possibilities of direct pattern transfer by mask projection, anisotropic etching with negligible damage, and etching with very high selectivity. Modifying the LDE-process by applying a microwave-excited gas results in more radicals and an increased etch rate. Some authors use Cl2 as the processing gas during the microwave-assisted laser dry etching (MALDE) with excimer laser radiation (248 nm) [1,2]. In this case the etch rate of Si(100) is below 1 A/pulse.

Channel fabrication technology has become increasingly important for microfluidic and nanofluidic devices. In particular, glass channels have high chemical and physical stability, high optical transparency, and ease of surface modification, so that there is increasing interest in glass microfluidic devices for chemical experiments in microfluidics and nanofluidics. For the fabrication of glass channels, especially those with a high aspect ratio (depth/width), lithography using a metal resist and dry etching have mainly been used. However, there are still issues involving the surface roughness of the etched channel and the low etching selectivity. In this study, a microchannel fabrication method with high etching selectivity that produces a smooth etched surface was developed. First, interference during dry etching by remaining Cr particles after the photolithography and Cr etching processes was assumed as the cause of the rough etched surface. Three different dry etching processes were introduced to verify this. In process 1 without removal of the Cr particles, the etched surface was not flat and had a 1 μm scale roughness. In process 2 where a cleaning process was included and high power etching was conducted, a smooth surface with a 1 nm scale roughness and a faster etching rate of 0.3 μm min−1 were obtained. For this high-power etching condition, the etching selectivity (fused silica/Cr) was relatively low at approximately 39–43. In process 3 with a cleaning process and low-power etching, although the etching rate was relatively low at 0.1 μm min−1, a smooth surface with 1 nm scale roughness (10 nm scale roughness deeper than 40 μm in the depth region) and a much higher etching selectivity of approximately 79–84 were obtained. The dry etching method presented in this study represents a significant contribution to microfluidics/nanofluidics for microchannel/nanochannel fabrication.

The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely the wet chemical etching method, using HNO3-HF-CH3COOH solution, and the Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching using inert gas only (e.g., argon gas), and ion chemical etching using an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning microscope (OSM) and Joel Scanning microscope (JSM). The formed hole width (ω) increases by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about ( 0.0707 and 0.0537 µm/min ) .Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. Normal 0 21 false false false MS X-NONE X-NONE The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely wet chemical etching method, using HNO3-HF-CH3COOH solution, and Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching used inert gas only (e.g., argon gas) while ion chemical etching used an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning Microscope (OSM) and Joel Scanning Microscope (JSM). The formed hole width (ω) increased by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about (0.0707 and 0.0537 µm/ min). Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

Summary form only given, as follows. Active Matrix Liquid Crystal Display (AMLCD) market is projected to quadruple in size by the next millennium. Within the last year, the flat panel display (FPD) marketplace has been very dynamic and the product requirements are evolving rapidly towards larger size, higher resolution, lower power consumption and at ever lower price targets. These market forces are driving FPD process technology innovations at a breathtaking pace. For FPD processing, dry etching is in an analogous position to that in IC processing back in the early 80s when the industry was posed to make the transition from wet to dry etch. Up to now, dry etching has only seen widespread manufacturing applications in Si and SiN processing. Within the last year, both Applied Komatsu Technology (AKT) and Lam Research (LRC) have introduced next generation FPD dry etch cluster tools. These tools offer improved process characteristics and enhanced capability that present many new opportunities to apply dry etching to FPD processing. In the next couple of years, dry etching will be a key enabler for architectural innovation. In the paper, these new dry etch processes and their applications in FPD display are reviewed.