In-process defect inspection and characterization study for dry etching chrome-on-quartz binary masks

The wet etching process in photomask fabrication could not meet requirements for small features for high density devices having optical proximity correction (OPC) features. Therefore, a dry etching process should be employed in mask making. However, there are some critical issues in dry etching process: one of the most important issues is critical dimension (CD) variation across the mask due to the loading effect during dry etching. CD errors caused by dry etch process are known to be originated from non-uniformity of plasma, non-vertical resist profile, and loading effect due to the various pattern densities. In case of loading effect, we are concerned about only macro-loading effect rather than micro-loading effect because the aspect ratio in the photomask is very small compared to that in the wafer. After dry etch, the patterns surrounded with large chrome area have large CDs because of the lower etch rate. We found that the macro-loading effect was about 5-10nm. And the effective range of the loading effect is amount to more than 10mm. In order to improve the CD variation caused from loading effect, we should optimize process conditions based on plasma uniformity, etch selectivity, resist profile, etc. However, it is a time consuming job. In this paper, we present a new method to improve loading effect, which is used for correcting e-beam proximity effect. Once we know the degree of loading effect, we can compensate it by allocating various doses at necessary locations.

Self-assembly block copolymers have drawn a lot of attention for its great potential on critical dimension (CD) control and line-edge roughness (LER) reduction, which become more and more crucial as the CD of transistors is only tens of nanometers nowadays. In this study, lamellar-forming poly(styrene-b-methyl methacrylate) copolymer which fabricates line patterns was chosen for its ability to provide higher aspect ratio and vertical sidewall profile in template stage, thus more suitable for the following etching process to substrate. A dry plasma etching process using pure oxygen and pure argon plasma as example chemical etching gas and physical etching gas, respectively, was studied. Etching selectivity and lateral etch rate, which are responsible for the final template height and CD loss, had been characterized on a capacitive reactive ion etching tool. The templates formed by the proposed process had high aspect ratios, excellent pattern fidelity, and low LER values. The PS lateral etch rate was small enough to provide a wide process window for retaining the CD of the pattern during the template forming process. Subsequent silicon etching using the PS template made by dry etching process yielded a steep and smooth sidewall profile.

Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (<200 °C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100% (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm2/V s) is not impacted by the etch process.

The incorporation of dry etch processes for mercury cadmium telluride (HgCdTe) infrared device fabrication is becoming critical for the infrared community as we advance toward the production of high-density devices. Dry etch processes are cleaner than wet etch processes. In addition, dry etches are highly anisotropic and are capable of producing the small features required by the more advanced device architectures. However, the incorporation of dry etch processes into device fabrication often affects the surface quality, producing roughened surfaces and variations in composition. Consequently, the identification of suitable dry etch processes to produce high quality infrared devices is essential. In this investigation, three different plasma etching tools (reactive ion etching, electron cyclotron resonance, and remote microwave) were used to etch HgCdTe with hydrogen. The hydrogen interaction with HgCdTe at similar etch depths was examined with spectroscopic ellipsometry and atomic force microscopy. Variations in surface roughness and composition obtained when etching with the three plasma etching tools are reported and the significance of energetic ions on surface quality is discussed.

Due to the advances in lithography and dry processing technologies it is now possible to fabricate devices with lateral dimensions in the nanometer range. Dry processes such as reactive ion etching (RIE) or chemically assisted ion beam etching (CAIBE), are generally required to provide the etch anisotropy needed to define such small structures. Unfortunately, the energetic ions in these ion beam processes introduce crystal damage which results in deterioration of electronic and optoelectronic properties of the semiconductor material. In order to exploit the full potential of the dry processes it is very important to characterize and understand the process-induced damage. This is particularly true in III-V semiconductor structures, where thermal annealing is often ineffective for restoring crystalline order. At present, the mechanism of damage introduction during dry etch processes is not clearly understood. The damage extends well beyond the calculated projected ion ranges. In addition, in RIE the energy and the flux of ions bombarding the etched wafer can only be controlled indirectly by adjusting the rf power, the pressure etc. Unless special techniques are used to measure the ion energy distribution, only the maximum possible ion energy is known from the value of the self-bias voltage. Also, in most situations the nature of the ions, their fluxes or the ion/neutral ratio are unknown. This lack of information further complicates the prediction of the extent of damage. Thus, the significance of characterization of dry etch induced damage in the fabrication of devices cannot be overemphasized. In this paper, we report the study of RIE-induced damage in the InAlAs/InGaAs material system which has great potential for applications in microwave devices and long-wavelength optical communications due to its excellent transport properties.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

InGaN-based light emitting diodes (LEDs) were fabricated through a photoelectrochemical (PEC) wet mesa etching process to replace the conventional dry mesa etching process. The undercut structures were formed from a bandgap-selective lateral wet etching process that occurred at the InGaN/GaN multiple-quantum-well layers. By measuring the selective-area microphotoluminescence spectra focused on the mesa edge region, the blueshift wavelength of the photoluminescence spectrum in the wet mesa etched light emitting diode (WME-LED) was 9.1 nm (55 meV) that was compared to the conventional dry etching LED. The relative internal quantum efficiencies of WME-LED were calculated as 13.7% (at the first region), 21.8% (at the second region), and 24.5% (at the third region) from the mesa center to the edge. The flatband voltage of the WME-LED was −13 V to balance the piezoelectric field, calculated as −1.17 MV/cm, in the InGaN active layer. However, we did not observe any flatband voltage in the conventional LED up to −19 V (piezoelectric field larger than −1.9 MV/cm). By forming the bending undercut structure on p-type GaN:Mg layer, the lattice mismatch induces a compressed strain and a piezoelectric field in the InGaN active layer that can be partially released in the WME-LED by using a PEC wet mesa etching process.

Channel fabrication technology has become increasingly important for microfluidic and nanofluidic devices. In particular, glass channels have high chemical and physical stability, high optical transparency, and ease of surface modification, so that there is increasing interest in glass microfluidic devices for chemical experiments in microfluidics and nanofluidics. For the fabrication of glass channels, especially those with a high aspect ratio (depth/width), lithography using a metal resist and dry etching have mainly been used. However, there are still issues involving the surface roughness of the etched channel and the low etching selectivity. In this study, a microchannel fabrication method with high etching selectivity that produces a smooth etched surface was developed. First, interference during dry etching by remaining Cr particles after the photolithography and Cr etching processes was assumed as the cause of the rough etched surface. Three different dry etching processes were introduced to verify this. In process 1 without removal of the Cr particles, the etched surface was not flat and had a 1 μm scale roughness. In process 2 where a cleaning process was included and high power etching was conducted, a smooth surface with a 1 nm scale roughness and a faster etching rate of 0.3 μm min−1 were obtained. For this high-power etching condition, the etching selectivity (fused silica/Cr) was relatively low at approximately 39–43. In process 3 with a cleaning process and low-power etching, although the etching rate was relatively low at 0.1 μm min−1, a smooth surface with 1 nm scale roughness (10 nm scale roughness deeper than 40 μm in the depth region) and a much higher etching selectivity of approximately 79–84 were obtained. The dry etching method presented in this study represents a significant contribution to microfluidics/nanofluidics for microchannel/nanochannel fabrication.

Summary form only given, as follows. Active Matrix Liquid Crystal Display (AMLCD) market is projected to quadruple in size by the next millennium. Within the last year, the flat panel display (FPD) marketplace has been very dynamic and the product requirements are evolving rapidly towards larger size, higher resolution, lower power consumption and at ever lower price targets. These market forces are driving FPD process technology innovations at a breathtaking pace. For FPD processing, dry etching is in an analogous position to that in IC processing back in the early 80s when the industry was posed to make the transition from wet to dry etch. Up to now, dry etching has only seen widespread manufacturing applications in Si and SiN processing. Within the last year, both Applied Komatsu Technology (AKT) and Lam Research (LRC) have introduced next generation FPD dry etch cluster tools. These tools offer improved process characteristics and enhanced capability that present many new opportunities to apply dry etching to FPD processing. In the next couple of years, dry etching will be a key enabler for architectural innovation. In the paper, these new dry etch processes and their applications in FPD display are reviewed.

Resists used in plasma processing

In this study, Cr defects resulted from high voltage E-beam writing in high Cr load Logic Mask were investigated. The Cr defect, which is a damage of anti-reflection layer on Cr, is mainly found in isolated Cr patterns of high Cr load Logic Mask. This defect appears under high voltage E-beam writing with high dose and dry etch process. High accelerating voltage and dose of E-beam writing decrease the thickness of remaining E-beam resist after developing. These phenomena are more significant in high Cr load Logic Mask consisted of isolated Cr patterns. Because the resist thickness of isolated Cr pattern is not enough for enduring dry etch process-induced damage, Cr surface is damaged during etching. Consequently, the Cr surface damage of high Cr load Logic Mask is related with voltage and dose of E-beam and dry etch process time. To prevent these defects, low accelerating voltage and dose of E-beam and low thickness of Cr layer to increase dry etch process margin are necessary.

As personal mobile devices have been improved and concept of IoT has been introduced into every objects as well as computers or tablet PCs, the importance of security for personal information has surfaced as a serious issue. For that reason, many related industries have been taking profound interests in fingerprint verification technology. One of the most attractive research should be manufacturing capacitive-typed fingerprint sensor array which is transparent and able to be embedded in the touch panel. The fingerprint sensor based on oxide thin film transistor (TFT) array is one of the solution for the high resolution and high speed operation. Furthermore, this transparent oxide TFT array has price competitiveness due to the simple structure and can be successfully adopted to the flexible IoT devices in comparison to the semiconductor technology based on the silicon.Since capacitive-typed high speed operation fingerprint sensor array consists of 500 ppi resolution pixels with one TFT and one capacitor, low resistance transparent electrode are essential to obtain high transparency. Well-known transparent electrode material, Indium-Tin-Oxide (ITO), has 10Ω/sq of sheet resistance at 150nm-thick that may not be enough to manufacture fingerprint sensor array embedded in the display panels. Representative low-resistance metal, Ag, has difficulty in use not only for electrode of oxide TFT but the sensing electrode due to its low transparency. Within the level that its transparency satisfies requirement, however, inserting Ag layer between both sides of ITO layers definitely helps resistance decreases.For the reduction of capacitance within the array, minimum width of electrode patterns used for the fingerprint sensor array is less than 5㎛ and dry etching process plays a vital role in patterning ITO/Ag/ITO triple layers. Although ITO and Ag can be etched in the same way by dry gas based on Cl, the difference on etch rates of the two materials possibly generates some problem like Ag exposure at the side of etched profile. It can surely cause a great change on the final properties of TFTs, and that is the reason why dry etching process should be a core technology in this case. As mentioned above, Cl2 and Ar are mainly used as etching gas for both ITO and Ag in this study [1], but their etch rates are greatly different from each other. We found out that ITO had been etched five times faster than Ag, so that a protrusion of Ag edge had been inevitable from the ITO edge during the triple dry etching sequences although we had put only 10nm-thick Ag in the middle. To solve this problem, we used two methods mostly to modify dry etching recipe for removing by-product that might be formed by Ag exposure in air; one is using O2 gas instead of Ar as a base gas during main etching, especially later in the process, the other is insertion of additional ashing step with O2gas after the main etching process.In this study, we fabricated top gate structured TFT applied with ITO/Ag/ITO triple stack as a source/drain in order to verify good characteristics of the triple layers as transparent electrode. As described above, we developed the dry etching conditions which didn’t have a bad effect on contact property, and also confirmed final characteristics of the top gate structured TFT. This top gate structured TFT included Indium-Gallium-Zinc-Oxide (IGZO) as an active layer and Al2O3as a gate insulator. TFT post annealed at 300℃ showed mobility, Von, S.S, and hysteresis of 15.6㎤/V.s, 0.3V, 0.1V/dec., and almost 0V, respectively, and moreover, study on stability and analysis depending on various dimensions of TFT channel will be proceeded. Furthermore, we are currently working on analysis of stacked films by TEM to investigate Ag film which may be degenerated during post annealed process or oxidized by exposure in air.Obtaining outstanding TFT properties with ITO/Ag/ITO triple stack as a source/drain layer means that we developed etched profile which does not influence TFT operation at all, and what is more, it can stand comparison with other transparent materials applied to fingerprint sensor embedded display panel. Besides, totally transparent high resolution transistor array will be fully valuable for new transparent display application such as augmented reality.[1] Y.J. Lee, S.D. Park, B.K. Song, S.-G Kim, H.-H, Choe, M.-P. Hong and G.-Y, Yeom, Jpn. J. Appl. Phys., Vol. 42 (2003) pp.286-290This work was supported by Open Innovation Lab Project from National Nanofab Center (NNFC).

In this study, the method for achieving precise CD MTT (critical dimension mean to target) in manufacturing attenuated PSM (phase shift mask) was investigated. As the specification for photomask becomes tighter, more precise control of CD is required. There are several causes to result in CD MTT error. In general mask patterning processes which are from blank material to dry etch, it is difficult to detect CD MTT error before final CD measurement and correct it. It is necessary to apply new process to mask production to correct CD error and control CD MTT precisely. Reducing number of factors which can have an effect on CD and introducing reliable method to correct CD error are important to achieve accurate CD MTT. For the correction of CD error, the reliability of CD in each measurement step such as resist CD or Cr CD before and after resist removal and effect on items related with CD like CD uniformity, isolated-dense CD difference, etc should be considered and evaluated. In this method to correct CD MTT error, Cr CD after removing resist was measured before MoSiN dry etch and additional corrective Cr dry etch using Cr CD information was applied to cancel CD error and then MoSiN dry etch was followed. In this case, factors affecting final CD are additional corrective Cr etch and MoSiN etch. The relationship between CD shift and corrective Cr etch time for masks with various pattern densities was found and necessary corrective Cr etch time was applied to CD correction process. The CD MTT error is canceled by additional corrective Cr dry etch step. As a result, accurate CD control and significant decrease of CD MTT error for attenuated PSM is achieved through the use of this CD correction method.

Origin of the dry etch damage in the short-channel oxide thin-film transistors for high resolution display application

Process optimizations have been done to produce 'Fine Pattern' reticles whose minimum target sizes are under 720 nm. 'Zero Bias' process for binary Cr reticles can be achieved with our dry etching process using ZEP-7000 blanks. MEBES-4500 exposure on resist films of 300 nm and dry etching with Magnetic Enhanced Reactive Ion Etching (MERIE) system are adopted. It is shown that adjusted develop condition weakens thinning effect of resist in sub-micron area due to proximity effect of exposure, and MERIE system with Gas Assist Etching (GAE) also improves pattern resolution. CD shift due to 'Loading Effect' is small and resist patterns are perfectly printed as Cr pattern with negligible deterioration of CD linearity. Much improved CD distribution in the area of 132 mm square can be obtained. In production of MoSiON-based attenuated-PSM (Att- PSM), CD shifts between Cr and MoSiON except OPC patterns (such as serif and scattering-bar) can be estimated about 30 nm. It is also shown that there are few defects after dry etching, and 'Zero Defect' reticles are obtained in most cases. Through the all results, validity and probability of our process to produce 'Fine Pattern Reticles' near the half- micron are discussed.

organic light‐emitting diode (OLED) can enable a greater artificial contrast ratio and viewing angle compared to liquid crystal display (LCD) because OLED pixels directly emit light. There is a shortcoming that the internal quantum efficiency can reach values close to 100%, but about 80% light disperses because of the difference among the refractive indices of the substrate, anode, indium tin oxide (ITO) film, and air. In this paper, three dimensions aspherical microlens arrays (3D A‐MLAs) with substrate modifications are developed to simulate the optical luminous field by using FRED software. This study modified parameters of 3D A‐MLAs such as the diameter, fill‐factor, aspect ratio, dry etching parameters, and electroforming rates of microlens to improve the extraction efficiency of the OLED. In dry etching, not only the aspect ratio with better extraction rate can be obtained by reactive ion etching (RIE) dry etching, but also an undercutting phenomenon can be avoided. The dimensions of 3D A‐MLAs can be accurately controlled in the electroforming process used to make a nickel‐cobalt (Ni‐Co) metal mold to achieve the designed dimensions. According to the measured results, the average luminance efficacy of the OLEDs with 3D A‐MLAs can be enhanced.