Reactive ion etching-induced damage in InAlAs/InGaAs heterostructures

The incorporation of dry etch processes for mercury cadmium telluride (HgCdTe) infrared device fabrication is becoming critical for the infrared community as we advance toward the production of high-density devices. Dry etch processes are cleaner than wet etch processes. In addition, dry etches are highly anisotropic and are capable of producing the small features required by the more advanced device architectures. However, the incorporation of dry etch processes into device fabrication often affects the surface quality, producing roughened surfaces and variations in composition. Consequently, the identification of suitable dry etch processes to produce high quality infrared devices is essential. In this investigation, three different plasma etching tools (reactive ion etching, electron cyclotron resonance, and remote microwave) were used to etch HgCdTe with hydrogen. The hydrogen interaction with HgCdTe at similar etch depths was examined with spectroscopic ellipsometry and atomic force microscopy. Variations in surface roughness and composition obtained when etching with the three plasma etching tools are reported and the significance of energetic ions on surface quality is discussed.

Chemically assisted ion beam etching (CAIBE) and reactive ion etching (RIE) are two popular dry etching techniques routinely used in the fabrication of submicron features. We have used both in situ and ex situ Raman spectroscopy to study the effects of dry etching on the depletion layer in heavily doped GaAs. We find that both CAIBE and RIE produce large numbers of traps that produce an insulating layer on the surface. CAIBE using ion energies greater than 2 keV also produces a damaged layer. For both techniques the use of chlorine based species reduces both traps and damage. Sputtering with chlorine alone, is shown to be able to eliminate both damage and traps. Finally, Raman spectroscopy is shown as a powerful in situ tool for studying etch damage.

Summary form only given. The talk will focus on the fabrication of 2D photonic crystals (PCs) in InP/InGaAsP/InP heterostructures by dry etching techniques with specific attention to Ar/Cl/sub 2/ based chemically assisted ion beam etching (CAIBE) and summarizes the ongoing research activities at the Royal Institute of Technology within the EU-IST project PCIC. It is demonstrated that Ar/Cl/sub 2/ CAIBE is a very promising method to obtain high aspect ratio etching of PCs in the InP-based materials. With this process, it is possible to obtain PC-holes as deep as 3 /spl mu/m even for feature (PC-hole) sizes as small as 200-250 nm. The critical role of the sample temperature, hence the chemical etching component, in determining geometric parameters of the PC-holes such as depth, side-wall profile (size and shape) is examined. It is shown that good quality PCs can be etched only when the chemical and physical components in the etch process are balanced. The role of the mask material and the dependence of etch-depth on feature size are discussed. Optical properties of the etched PCs are used to evaluate the quality of the etched PCs and thereby identify the most promising dry etching processes and process conditions. Finally, limitations of reactive ion etching using hydrocarbon-based chemistry for PC fabrication in the InP system will be highlighted.

The wet etching process in photomask fabrication could not meet requirements for small features for high density devices having optical proximity correction (OPC) features. Therefore, a dry etching process should be employed in mask making. However, there are some critical issues in dry etching process: one of the most important issues is critical dimension (CD) variation across the mask due to the loading effect during dry etching. CD errors caused by dry etch process are known to be originated from non-uniformity of plasma, non-vertical resist profile, and loading effect due to the various pattern densities. In case of loading effect, we are concerned about only macro-loading effect rather than micro-loading effect because the aspect ratio in the photomask is very small compared to that in the wafer. After dry etch, the patterns surrounded with large chrome area have large CDs because of the lower etch rate. We found that the macro-loading effect was about 5-10nm. And the effective range of the loading effect is amount to more than 10mm. In order to improve the CD variation caused from loading effect, we should optimize process conditions based on plasma uniformity, etch selectivity, resist profile, etc. However, it is a time consuming job. In this paper, we present a new method to improve loading effect, which is used for correcting e-beam proximity effect. Once we know the degree of loading effect, we can compensate it by allocating various doses at necessary locations.

Self-assembly block copolymers have drawn a lot of attention for its great potential on critical dimension (CD) control and line-edge roughness (LER) reduction, which become more and more crucial as the CD of transistors is only tens of nanometers nowadays. In this study, lamellar-forming poly(styrene-b-methyl methacrylate) copolymer which fabricates line patterns was chosen for its ability to provide higher aspect ratio and vertical sidewall profile in template stage, thus more suitable for the following etching process to substrate. A dry plasma etching process using pure oxygen and pure argon plasma as example chemical etching gas and physical etching gas, respectively, was studied. Etching selectivity and lateral etch rate, which are responsible for the final template height and CD loss, had been characterized on a capacitive reactive ion etching tool. The templates formed by the proposed process had high aspect ratios, excellent pattern fidelity, and low LER values. The PS lateral etch rate was small enough to provide a wide process window for retaining the CD of the pattern during the template forming process. Subsequent silicon etching using the PS template made by dry etching process yielded a steep and smooth sidewall profile.

organic light‐emitting diode (OLED) can enable a greater artificial contrast ratio and viewing angle compared to liquid crystal display (LCD) because OLED pixels directly emit light. There is a shortcoming that the internal quantum efficiency can reach values close to 100%, but about 80% light disperses because of the difference among the refractive indices of the substrate, anode, indium tin oxide (ITO) film, and air. In this paper, three dimensions aspherical microlens arrays (3D A‐MLAs) with substrate modifications are developed to simulate the optical luminous field by using FRED software. This study modified parameters of 3D A‐MLAs such as the diameter, fill‐factor, aspect ratio, dry etching parameters, and electroforming rates of microlens to improve the extraction efficiency of the OLED. In dry etching, not only the aspect ratio with better extraction rate can be obtained by reactive ion etching (RIE) dry etching, but also an undercutting phenomenon can be avoided. The dimensions of 3D A‐MLAs can be accurately controlled in the electroforming process used to make a nickel‐cobalt (Ni‐Co) metal mold to achieve the designed dimensions. According to the measured results, the average luminance efficacy of the OLEDs with 3D A‐MLAs can be enhanced.

Surface damage in Si substrates created by Ar-ion milling or by reactive-ion etching in CF4, CHF3, Cl2, SiCl4, or SiF4 has been investigated. Metal-oxide-semiconductor capacitors were fabricated on the etched Si substrates, and the interface-state densities were obtained from capacitance-voltage measurements. Interface states generated by the dry etching processes were strongly dependent on the etching gas and the bias voltage. Carbon-based gases (CF4, CHF3) induced more interface states than those without carbon. For the carbon-based gases, Si samples etched in CHF3 showed lower densities of interface states than samples etched in CF4 under the same conditions. Generation lifetime measurements indicated that samples with large densities of interface states also had short lifetimes. Measurements of oxidation-induced stacking faults caused by dry etching were consistent with both the interface-state and lifetime measurements. Thermal annealing of the etched wafers was not effective in reducing the surface damage. The measured interface states on the dry etched Si substrates could be lowered to their pre-etched levels by removing at least 500 Å of the etched surface by wet chemical etching.

Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (<200 °C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100% (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm2/V s) is not impacted by the etch process.

Wet chemical, reactive ion etching and reactive ion-beam etching of sol-gel prepared PZT (54/46) [Pb(Zr,Ti)O3], Lanthanum doped PZT [PLZT (9/65/35)] and LiTaO3 have been investigated. Wet chemical etching using an HCI-HF solution, reactive-ion etching using a SF6 plasma and chemically assisted ion-beam etching (CAIBE) using a xenon plasma and chlorine reactive gas were used. Etch rates for each method were determined and the ability to define small features in the thin film ferroelectric was investigated. It was found that for structures smaller than approximately 20 × 20 μm2, chemically assisted ion beam etching provided by far the best results. 3 × 3 μm2 capacitor and 2 μm wide optical waveguide structures in PZT, PLZT respectively, were successfully fabricated using a CAIBE system. An etch depth monitor enabled accurate in-situ etch rate monitoring of the PLZT and PZT thin films.

Within this decade, there has been immense effort focused on reducing the cost of energy storage devices. The goal towards energy independence through electrification of automobiles for widespread adoption has greatly incentivized this endeavor. Strategies ranging from novel materials investigation to advanced device manufacturing development span the cost reduction effort. Maxwell Technologies is actively engaged in this global effort from the direction of dry electrode fabrication technology. Maxwell dry electrode technology offers manufacturing cost and performance competitiveness, and novel battery chemistry enablement. This paper provides the initial foundation and validation for the application of dry coated electrode in lithium-ion batteries. Maxwell Technologies is a San Diego based ultracapacitor manufacturer that uses a proprietary liquid-free electrode production process. Advanced process development without the need for solvents has enabled Maxwell’s dry electrode production lines to operate at high throughput using a minimal manufacturing footprint. This unique electrode manufacturing process does not introduce any volatile waste products into the atmosphere or require complex manufacturing plant arrangement. It begins with dry raw materials compounding and maintains its liquid-free state throughout the subsequent processing steps to ultimately produce a robust high-performance ultracapacitor electrode. Maxwell is currently engaged in research and development efforts to expand the application space of its dry electrode process technology to include battery electrode manufacturing. Cell performance using prototype dry coated lithium-ion battery electrodes has been demonstrated. Electrode configuration with various architectures using a wide range of materials can be produced at thicknesses ranging from about 50 microns to about 1 millimeter. In addition to manufacturing flexibility, the cohesion and adhesion properties of electrodes derived from the dry process are superior in the presence of electrolyte at high temperatures compared to those produced using the wet coating technology. This unique electrode process technology offers significant saving in manufacturing cost and helps curb CO2 pollution during the battery electrode manufacturing process. By eliminating the use of any liquids/solvents, and the associated coating and drying complexity inherent in wet processing, the dry electrode process is environmentally friendly, and can be readily installed and commissioned with a much lower start-up capital investment. Thus, dry electrode manufacturing is economically attractive and socially responsible. This paper will provide recent progress in high energy dry electrode coating technology and its capacity for the enablement of advanced battery chemistries, and cell performance results derived from dry coated lithium-ion battery electrodes.

In this study, Cr defects resulted from high voltage E-beam writing in high Cr load Logic Mask were investigated. The Cr defect, which is a damage of anti-reflection layer on Cr, is mainly found in isolated Cr patterns of high Cr load Logic Mask. This defect appears under high voltage E-beam writing with high dose and dry etch process. High accelerating voltage and dose of E-beam writing decrease the thickness of remaining E-beam resist after developing. These phenomena are more significant in high Cr load Logic Mask consisted of isolated Cr patterns. Because the resist thickness of isolated Cr pattern is not enough for enduring dry etch process-induced damage, Cr surface is damaged during etching. Consequently, the Cr surface damage of high Cr load Logic Mask is related with voltage and dose of E-beam and dry etch process time. To prevent these defects, low accelerating voltage and dose of E-beam and low thickness of Cr layer to increase dry etch process margin are necessary.

With the inherent advantages of good Critical Dimension (CD) control and good pattern fidelity, dry etching of Chrome-on- Quartz (COG) binary masks is necessary for production of 0.18um or below technology generation masks. Chrome dry etching process, however, tends to produce more defects than the traditional wet etch processes. We have conducted in-process defect inspection studies, which have identified several defect sources and have proposed process controls that minimize the number and size of defects from the entire dry etch process. This paper discusses the design of a defect test vehicle and describes an approach and methodology of defect inspection as a means of understanding the creation mechanisms of process related defects. A Lasertec Corporation (i)-line inspection system is employed along with different microscopy and metrology tools to identify and characterize these defects that can be attributed to the various steps in this entire dry etch process. Our results demonstrate that this approach of in-process inspection is very effective at identifying defects and their sources as they become evident at different process steps.

Graded-index separate-confinement heterostructure (GRINSCH) strained-layer lasers with five In/sub 0.3/Ga/sub 0.7/As quantum wells have been fabricated with cavity lengths from 50 to 400 mu m using chemically assisted ion-beam etching (CAIBE) to form the laser mirrors. The dry-etching process is thermally assisted, which gives a reproducible etching rate. A minimum threshold-current value is observed at a cavity length of 50 mu m, showing that the multiquantum-well design is optimum for short-cavity lasers. A relaxation oscillation frequency of 10 GHz and a -3 dB bandwidth of 15 GHz have been measured on a 200*10 mu m mesa-structure device.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dry etching processes routinely used for plasma etching of crystalline Si (c-Si) are evaluated as potential means for removal of porous Si (PS). Etching rates for PS and the selectivity with respect to c-Si are determined for a variety of plasma conditions and material parameters. We find that PS etching rates depend on the plasma conditions, and more importantly on PS material properties such as porosity and degree of oxidization. In addition, the selectivity varies from high to very low values, depending on the porosity and the thermal treatment of PS. The developed dry etching processes are compatible with the fabrication of devices where PS is used both as a sacrificial layer and as a patternable active material.

As personal mobile devices have been improved and concept of IoT has been introduced into every objects as well as computers or tablet PCs, the importance of security for personal information has surfaced as a serious issue. For that reason, many related industries have been taking profound interests in fingerprint verification technology. One of the most attractive research should be manufacturing capacitive-typed fingerprint sensor array which is transparent and able to be embedded in the touch panel. The fingerprint sensor based on oxide thin film transistor (TFT) array is one of the solution for the high resolution and high speed operation. Furthermore, this transparent oxide TFT array has price competitiveness due to the simple structure and can be successfully adopted to the flexible IoT devices in comparison to the semiconductor technology based on the silicon.Since capacitive-typed high speed operation fingerprint sensor array consists of 500 ppi resolution pixels with one TFT and one capacitor, low resistance transparent electrode are essential to obtain high transparency. Well-known transparent electrode material, Indium-Tin-Oxide (ITO), has 10Ω/sq of sheet resistance at 150nm-thick that may not be enough to manufacture fingerprint sensor array embedded in the display panels. Representative low-resistance metal, Ag, has difficulty in use not only for electrode of oxide TFT but the sensing electrode due to its low transparency. Within the level that its transparency satisfies requirement, however, inserting Ag layer between both sides of ITO layers definitely helps resistance decreases.For the reduction of capacitance within the array, minimum width of electrode patterns used for the fingerprint sensor array is less than 5㎛ and dry etching process plays a vital role in patterning ITO/Ag/ITO triple layers. Although ITO and Ag can be etched in the same way by dry gas based on Cl, the difference on etch rates of the two materials possibly generates some problem like Ag exposure at the side of etched profile. It can surely cause a great change on the final properties of TFTs, and that is the reason why dry etching process should be a core technology in this case. As mentioned above, Cl2 and Ar are mainly used as etching gas for both ITO and Ag in this study [1], but their etch rates are greatly different from each other. We found out that ITO had been etched five times faster than Ag, so that a protrusion of Ag edge had been inevitable from the ITO edge during the triple dry etching sequences although we had put only 10nm-thick Ag in the middle. To solve this problem, we used two methods mostly to modify dry etching recipe for removing by-product that might be formed by Ag exposure in air; one is using O2 gas instead of Ar as a base gas during main etching, especially later in the process, the other is insertion of additional ashing step with O2gas after the main etching process.In this study, we fabricated top gate structured TFT applied with ITO/Ag/ITO triple stack as a source/drain in order to verify good characteristics of the triple layers as transparent electrode. As described above, we developed the dry etching conditions which didn’t have a bad effect on contact property, and also confirmed final characteristics of the top gate structured TFT. This top gate structured TFT included Indium-Gallium-Zinc-Oxide (IGZO) as an active layer and Al2O3as a gate insulator. TFT post annealed at 300℃ showed mobility, Von, S.S, and hysteresis of 15.6㎤/V.s, 0.3V, 0.1V/dec., and almost 0V, respectively, and moreover, study on stability and analysis depending on various dimensions of TFT channel will be proceeded. Furthermore, we are currently working on analysis of stacked films by TEM to investigate Ag film which may be degenerated during post annealed process or oxidized by exposure in air.Obtaining outstanding TFT properties with ITO/Ag/ITO triple stack as a source/drain layer means that we developed etched profile which does not influence TFT operation at all, and what is more, it can stand comparison with other transparent materials applied to fingerprint sensor embedded display panel. Besides, totally transparent high resolution transistor array will be fully valuable for new transparent display application such as augmented reality.[1] Y.J. Lee, S.D. Park, B.K. Song, S.-G Kim, H.-H, Choe, M.-P. Hong and G.-Y, Yeom, Jpn. J. Appl. Phys., Vol. 42 (2003) pp.286-290This work was supported by Open Innovation Lab Project from National Nanofab Center (NNFC).