Reversible binary subtractor design using quantum dot-cellular automata

Quantum dot Cellular Automata (QCA) is a nanotechnology which offers an attractive solution to overcome the physical limits that CMOS devices faces during further downscaling of their dimensional sizes. In QCA, the electrons are basically restrained in quantum dots. The fundamental basic gates in QCA are the Majority Gate (MG) and the Inverter. Further downscaling of the dimensions of CMOS devices is more and more challenging, as reduction in feature size of CMOS devices has reached to its feature size limit. So we use QCA which provides powerful features such as higher packaging density, reduced area, much lower power dissipation and higher switching speeds at nanometer scale. QCA designs new logic circuits which are translations of standard logic devices. Here in this paper we proposed QCA implementation of binary to gray code converter.

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

The atomistic quantum-dot cellular automata (QCA) based implementations of the reversible circuits have got tremendous exposures in the last few days, due to “room-temperature workability” of the QCA. The researchers are in serious need of a methodology that can realize the area-efficient QCA counterparts of reversible benchmark circuits. In this work, a novel methodology named majority-layered T hybridization is proposed to synthesize the reversible circuits using QCA. Firstly the reversible library consisting of CNTS Gates have been generated to validate the usability of the proposed methodology. Then, an elementary QCA module of 3×3 Toffoli Gate have been proposed and extended in the realization of 4×4, 5×5 and 6×6 Toffoli Gates (multi-control Toffoli Gates). The proper mathematical modelling of the several QCA design metrics like effective area, delay and O-cost has been established. The QCA counterpart of 3×3 Toffoli Gate reports 18.61% less effective area and 8.33% less O-cost compared to th...

According to recent research, with the ever-increasing use of Internet of Things (IoT) devices, there has arisen an ever-growing need for high-performance yet low-power circuits that can efficiently process information. Quantum-dot Cellular Automata (QCA) has emerged as a promising alternative to conventional complementary metal-oxide-semiconductor (CMOS) technology due to its great potential in digital design at nanoscale levels on account of very low power consumption and very high processing speed. However, QCA circuits are inherently prone to faults due to variations in manufacturing processes and due to the influence of environmental factors. These faults degrade the performance of a QCA circuit considerably. Hence, fault tolerance is one of the major factors of consideration while designing a QCA circuit, particularly when the application requires very reliable and continuous operation, say in an IoT system. As such, this work presents a fault tolerant Carry Skip Adder (CSA) for QCA-based circuits. The fault tolerance of basic arithmetic components of IoT nodes performing tasks corresponding to the signal processing, control, and data manipulations is enhanced in the proposed architecture. The area occupied by a fault-tolerant full-adder circuit is 0.06 μm² and a clock cycle is 0.75; its core will be used in the CSA design. It realizes fault-tolerant multiplexers (MUX) and a majority gate, which gives the same result when there is a missing or extra single-cell fault. The most astonishing characteristic of this transistor-based CSA is its 85% tolerance for different types of failures. The CSA with three layers contains 1542 quantum cells, 4.75 clock phases, and occupies an area of 4.59 μm². It is compact and efficient architecture; therefore, it is very suitable for IoT applications where the area constraint and power efficiency are the key issues. The proposed CSA will increase the robustness and reliability of QCA-based digital circuits by integrating fault tolerance into its design such that the circuitry based on QCA can keep their functionality on even in fault-prone environments.

A communication system is implemented as quantum-dot cellular automata. The advance method of Nano technology is Quantum-dot cellular automata (QCA). QCA is a promising alternative to the current CMOS technology. It can be implemented at the Nano scale, reaching ultra-low power consumption. Communication systems are important in current computer systems and it is expected to be even more important in near future. In a bottom-up approach, the Parallel-to-Serial and Serial-to-Parallel converters were described, which are essential to the serial communication. The components for robust communication, such as QCA circuits for Hamming code and Parity Checker are used. The coplanar QCA crossover architecture is used in the design of QCA that leads to the reduction of QCA cell count and area consumption. Reversible Logic design is also used. Reversible logic is found to be Low power design which becomes emerging technology in Low power Nanotechnology era. In this work they devoted to design a Reversible Logic Gate which is a universal gate and can be design with alternative of co-planer cross over wire. They introduce a passive type 3×3 tile that will also helpful for design the co-planner crossover wire.

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively.

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This paper presents the design and simulation of a 16-bit $\times 32$ -bit SRAM with a new structure in QCA. Since QCA is a pipeline, this SRAM has a high operating speed. The 16-bit $\times 32$ -bit SRAM has a new structure with a 32-bit width designed and implemented in QCA. It has the ability of a conventional logic SRAM that can provide read/write operations frequently with minimum delay. The 16-bit $\times 32$ -bit SRAM is generalized and an $n\times 16$ -bit $\times 32$ -bit SRAM is implemented in QCA. Novel 16-bit decoders and multiplexers (MUXs) in QCA are presented that have been designed with a minimum number of majority gates and cells. The new SRAM, decoders, and MUXs are designed, implemented, and simulated in QCA using a signal distribution network to avoid the coplanar problem of crossing wires. The QCA-based SRAM cell was compared with the SRAM cell based on CMOS. Results show that the proposed SRAM is more efficient in terms of area, complexity, clock frequency, latency, throughput, and power consumption.

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

Heat dissipation is one of the major problems in the construction of electronic devices. Reversible computing is one of the emerging computing paradigms to overcome heat dissipation problem. One of the nanoscale devices that has low power consumption and can be used to construct digital logic components is quantum-dot cellular automata (QCA). In this paper, the benefits of reversible computing of QCA will be used to propose QCA designs for two main reversible gates, the CNOT and the TOFFOLI gates. The proposed CNOT gate has been used to design QCA for double CNOT gate to show its reversibility, and QCA design for the SWAP circuit that contains 3 CNOT gates. The suggested TOFFOLI gate is utilized to construct QCA for double TOFFOLI gate and a reversible circuit which consists of several reversible gates. The suggested QCA designs for double CNOT, double TOFFOLI and reversible circuits such as SWAP circuit have been proposed by adding cells with certain clocks to the wires that connects the proposed gates. The proposed QCA designs show better cell count, area used in the construction, number of majority gate, wire crossover, and/or clock cycle delay when compared with relevant designs in literature.

This paper proposes a radical approach to designing nanoscale Quantum Dot Cellular Automata (QCA) designs by leveraging CMOS design tools such as those used for logic validation. Based on design rules that guarantee deterministic digital behavior of QCA designs, we identified a finite set of legal arrangements for QCA cells. These cell arrangements can be composed to yield robust QCA building block gates (majority gate and inverters) and interconnect structures. On one hand, such a hierarchical building blocks approach can be used to synthesize large scale, robust QCA designs. On the other hand, as shown in this paper, such a hierarchical building blocks approach can be used to check if QCA designs follow the robust design rules. If so, the implemented digital logic function can be extracted, translated into an equivalent Verilog or VHDL netlist, and validated using commercial CMOS design validation tools. Towards demonstrating the proposed approach, we designed a 2-bit QCA adder, extracted the digital logic, stored it in a common engineering database (OpenAccess) and validated the functionality using ModelSim CMOS simulator.

Abstract—Quantum Dot Cellular Automata (QCA) is an eminent nano-technology and solution of Complementary Metal Oxide Semiconductor (CMOS) for it’s computation and transformation procedure. It is attractive for it’s size, faster speed, high scalable feature, low power consumption and higher switching frequency compared to CMOS technology. Reversible logic has many factual operation in QCA as well as VLSI design, nanotechnology, digital signal processing (DSP). This paper presents a systematic design of reversible gate based on QCA. A modified pattern of Fredkin gate, MCL gate and a new scheme of URG gate, BJN gate is proposed in this paper. For design and verification QCADesigner, a widely used simulation tool is employed. The proposed circuits can be used in erecting of nano scale low power information processing system and modelingcomplex computing systems.

Quantum Dot Cellular Automata (QCA) is an emerging and promising technology. When CMOS technology faces serious challenges, the nanotechnology comes into play. QCA overcomes the limitations of CMOS technology and thus capable of replacing the CMOS technology. This article presents a 2 Dot 1 Electron QCA design methodology of reversible 2 : 1 MUX. In our present scope, we concentrate only on the logical reversibility of the design. Logical reversibility implies a one-to-one mapping between the inputs and the outputs of the construct. To the best of our knowledge, a reversible 2 : 1 MUX design has not been reported yet using 2 Dot 1 Electron QCA.

Regular clocking-based Automated Cell Placement technique in QCA targeting sequential circuit

An optimized arithmetic logic unit in quantum-dot cellular automata (QCA) technology