Regular clocking-based Automated Cell Placement technique in QCA targeting sequential circuit

Quantum‐dot cellular automata (QCA) is gaining worldwide popularity due to its higher device concentration, lower power indulgence, and better switching speed. The information flows in QCA with the polarization state defined by the placement of electrons instead of current flow. The cell interaction principle under the influence of the clocking zone controls the cell placement during QCA circuit design. Most of the designs reported so far used random cell placement, which has no fabricating sense. Moreover, it is equally important for a cell placement algorithm to follow a realistic, regular underlying clocking scheme to maintain proper routing channels. In this regard, a systematic cell placement for the combinational logic circuit in QCA is proposed using the widely accepted underlying regular clocking scheme, universal, scalable and efficient (USE). The proposed method traverses all possible paths of a combinational logic circuit from output to input to build the desired circuit generating the automatic cell layout. A grid of clock zone of USE clock scheme is considered in the initial layout driving different paths of the circuit and finally evolves as the desired circuit. The generated automatic QCA layouts are competitive in occupied area, delay, and its cell count, which advocates the significance of such a scheme.

The quantum-dot cellular automata (QCA) paradigm is a revolutionary approach to molecular-scale computing which represents binary information using the charge configuration of nanostructures in lieu of current switching devices. The basic building-block of QCA devices is the QCA cell. Electrostatic interaction between neighboring cells allows the design of QCA wires, logic devices and even simple microprocessors. The geometry of molecular six-dot QCA cells enables the clocking of QCA device via an electric field generated by a layout of clocking wires. Thus, precise control over the timing and direction of data flow in QCA circuits is possible. The design of QCA circuits now lies not only in the logic structure of the cells, but also in the layout of clocking wires. We discuss the clocking of QCA devices and connect layout to architecture.

Quantum‐dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit designs. The circuits in QCA have been extensively studied, which suffer from negative impacts due to the limits of the manual design process, even for a modest complexity. In the process of QCA circuit design, the problems caused by clock distribution and long transmission lines have to be considered. In order to solve such problems, some researchers have proposed several clock schemes and expected to realise electronic design automation. These clock schemes, however, have drawbacks; the most important one is the limitation of flexibility on designing complex circuits. In this regard, this study proposes a convenient, flexible, and efficient (CFE) clocking scheme by using diamond structures for clock zones, each of which has the same neighbouring clock zone and four information transmission directions. It has main advantages of existing clocking schemes and can commendably increase the flexibility in circuit design process. In order to show the suitability of the proposed CFE scheme using standard clock mechanism in QCA, several types of circuits proposed in this study reveal its advantages in comparison with an existing state‐of‐the‐art clocking scheme.

A general and efficient clocking scheme for majority logic in quantum-dot cellular automata

Quantum dot Cellular Automata (QCA) is a nanotechnology which offers an attractive solution to overcome the physical limits that CMOS devices faces during further downscaling of their dimensional sizes. In QCA, the electrons are basically restrained in quantum dots. The fundamental basic gates in QCA are the Majority Gate (MG) and the Inverter. Further downscaling of the dimensions of CMOS devices is more and more challenging, as reduction in feature size of CMOS devices has reached to its feature size limit. So we use QCA which provides powerful features such as higher packaging density, reduced area, much lower power dissipation and higher switching speeds at nanometer scale. QCA designs new logic circuits which are translations of standard logic devices. Here in this paper we proposed QCA implementation of binary to gray code converter.

If an external point charge and the movable charges of an isolated quantum-dot cellular automata (QCA) cell have the same polarity, the point charge greatly affects the polarization (P) of the cell only when it is in a narrow band with periodically changing width. The center of the band is on a radiusR circle. The ratio ofR to the electric charge (q) is a constant determined by the paremeters of the cell. A QCA cell can be used as charge detector based on the above phenomenon.

As CMOS technology has a scaling limitation in deep nanometer technologies, the best alternative for CMOS technology is a Quantum - Dot Cellular Automata (QCA) technology. Quantum dot Cellular Automata has the combined nature of both quantum mechanics and cellular automata. The QCA technology has many advantages than transistor based technology such as small size, high speed, and low power consumption. The working principle of QCA technology is at the molecular level. In conventional CMOS technology, transistors are used to create a logic gate. But in QCA technology, QCA cells are used to create logic gates and wire. The basic logic elements are an inverter and the majority gate. By using these elements many of the combinational and sequential circuits are created. In this brief, we propose the binary up counter using T flip flop. 2 bit and 3 bit Counters are implemented using the above mentioned QCA technology. The layout was designed and the functionality of the counter circuit was verified using QCADesigner tool.

Quantum Dot Cellular Automata (QCA) is an alternative to CMOS technology. The other technologies proposed by researchers are FINFET, CNTs and MTJ to reduce scalability of CMOS devices. Using Quantum Dot Cellular Automata, the low power, extremely dense circuits are designed. QCA cell is the fundamental unit in building logic gates. These cells are powered using specific clock. QCA cells are used to design basic gates and to realize Boolean expressions. QCA Designer tool is used to carry out simulations. The simulation results are same as theoretical results. The complexity and size of circuits are reduced using QCA. The paper includes design of Programmable Logic Array (PLA).

This study presents an innovative single-layered toggle flip-flop with highly polarized output designed specifically for Quantum-dot Cellular Automata (QCA), a cutting-edge nanocomputing approach. Building on the capabilities of this advanced flip-flop, a two-bit asynchronous down (ripple) counter was developed using QCADesigner 2.0.3, all within the QCA framework. The counter exhibits exceptional scalability and reliability, addressing key challenges in QCA circuit design. Energy efficiency and cost-effectiveness are standout features of the design, with a 53% improvement in energy efficiency and a 38% reduction in QCA-specific cost, as verified by QCADesigner-E 2.2 simulations. Furthermore, the physical stability of the proposed circuit was thoroughly examined through kink energy calculations, highlighting its robustness. These optimizations were achieved by avoiding complex crossovers and leveraging the benefits of the enhanced flip-flop architecture. The results underscore the significant potential of QCA in improving digital circuit performance, paving the way for more efficient, scalable, and cost-effective nanoelectronic designs and pushing the boundaries of next-generation nanocomputing solutions.

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

Some people believe that IC densities are approaching the fundamental limits inherent to semiconductor technologies. One alternative to semiconductors is Quantum-dot Cellular Automata (QCA); QCA is a nanotechnology that offers the potential to build denser IC's that switch at higher frequencies and run on lower power. QCA's most basic building block, the QCA cell, is inherently binary; digital circuits are implemented by arranging these QCA cells in pre-defined configurations on a two dimensional plane. This paper proposes a logic formulation that describes arranging QCA cells on a two dimensional plane; it is presented as a set of rules that can be implemented with basic Boolean variables and operators. This Boolean formulation is general and can be applied to any given specification. In addition, an optimization constraint is defined so that the logic formulation will only validate the most efficient QCA cell arrangements. The correctness of the logic formulation has been empirically verified by testing it with a SAT solver. The effectiveness of the minimization constraint in conjunction with the logic formulation has been tested with a Pseudo-Boolean ILP solver.

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively.

Conventional CMOS technology comes up with a percentage of margins when climbing into a nano-level. So to overcome this, several substitute technologies have been proposed as a solution. Quantum dot Cellular Automata (QCA) technology is one such upcoming nano-technology that can be a perfect substitute of Complementary Metal Oxide Semiconductor (CMOS) due to its low power consumption and high speed in both nano-science and nano-electronics arena. Thus, QCA overpowers the hitches of CMOS technology and has a substantial relevance in the field of quantum computation. Literary study deficits in hazard free design of QCA circuits. Hazard in a system are undesirable effects which create uncertain outputs and can be avoided. In this article, static hazard has been focused for QCA circuit where 2:1 multiplexer is the experimental object. Both the hazardous and hazard-free multiplexers have been designed, analyzed, compared and finally the better one has been proposed. All designs have been confirmed using QCADesigner simulation tool.

Utilizing charge reconfigurations of quantum-dot cells in building blocks to design nanoelectronic adder circuits

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.