Parallel FIR filters based on modulo arithmetic

Parallel FIR filter is the need of many low power and high speed DSP applications. In this paper, fast FIR algorithm based parallel symmetric FIR filter using Han-Carlson adder based vedic multiplier is proposed. FFA algorithm reduces the multiplier count as compared to the traditional parallel design. In order to improve the performance of the proposed filter, recently developed Han-Carlson adder based Vedic multiplier is used. In the proposed design the adder unit is also implemented using Han-Carlson adder. In the proposed design two and three parallel FIR filters of order 24 and 72 are implemented using VHDL. The implementation results show that the proposed architecture provides low critical path delay and power dissipation as compared to the conventional one. With the advantage of low delay and power, proposed architecture is useful in modern signal processing and communication applications.

Based on fast FIR algorithms (FFAs), this brief proposes new parallel FIR filter architectures, which are beneficial to symmetric convolutions of odd length in terms of the hardware cost. The proposed parallel FIR architectures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in the subfilter section at the expense of increase in adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area, and in addition, the overhead from the increase in adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a three-parallel 81-tap filter, the proposed structure saves 26 multipliers at the expense of five adders, whereas for a three-parallel 591-tap filter, the proposed structure saves 196 multipliers at the expense of five adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large.

Filters play a vital role in information and communication technology. This project proposes a less complexity FFA based parallel FIR filter design and implementation. This paper proposes the design of fast parallel filter with the block sizes L=2,3 and 4 respectively. By employing parallelism two or more number of samples are processed at each clock cycle which can be effectively used for multirate applications. The number of complex multiplications are reduced by employing polyphase decomposition. Here for all the cases, the overall filter output responses is decomposed in to several sub parts which includes sub filters and adders used before and after filters. The computational complexity is reduced for the fast parallel FIR filter when compared to the conventional parallel FIR filter. The simulation is done in Verilog with cyclone II family and EP2C70F672C6 device and EP2C35F672C6 device. The hardware implementation is done with Altera DE2 board and the results are reported. The results shows that the fast parallel filtering is efficient in terms of computational complexity

As more cloud computing resources are used for machine learning training and inference processes, privacy-preserving techniques that protect data from revealing at the cloud platforms attract increasing interest. Homomorphic encryption (HE) is one of the most promising techniques that enable privacy-preserving machine learning because HE allows data to be evaluated under encrypted forms. However, deep neural network (DNN) implementations using HE are orders of magnitude slower than plaintext implementations. The use of very long polynomials and associated number theoretic transform (NTT) operations for polynomial multiplications is the main bottlenecks of HE implementation for practical uses. This article introduces RRAM number theoretic transform (RM-NTT): a resistive random access memory (RRAM)-based compute-in-memory (CIM) system to accelerate NTT and inverse NTT (INTT) operations. Instead of running fast Fourier transform (FFT)-like algorithms, RM-NTT uses a vector-matrix multiplication (VMM) approach to achieve maximal parallelism during NTT and INTT operations. To improve the efficiency, RM-NTT stores modified forms of the twiddle factors in the RRAM arrays to process NTT/INTT in the same RRAM array and employs a Montgomery reduction algorithm to convert the VMM results. The proposed optimization methods allow RM-NTT to significantly reduce NTT operation latency compared with other NTT accelerators, including both CIM and non-CIM-based designs. The effects of different RM-NTT design parameters and device nonidealities are also discussed.

Based on fast convolution algorithm, this paper proposes improved parallel FIR filter structures for linear-phase FIR filters where the number of taps is a multiple of parallelism. The proposed parallel FIR structures not only use fast convolution algorithm to reduce the number of subfilter, but also exploit the symmetric (or antisymmetric) coefficients of linear-phase FIR filter to reduce half the number of multiplications in subfilter section at the expense of additional adders in preprocessing and postprocessing blocks. The proposed parallel FIR structures save a large amount of hardware cost for symmetric (or antisymmetric) coefficients from the reported FFA parallel FIR filter structures, especially when the length of the filter is large, e.g., the proposed 4-parallel FIR filter structure has eight subfilter blocks in total and four subfilter blocks contain symmetric coefficients, whereas the improved FFA structure has nine subfilter blocks in total and four contain symmetric coefficients. Specifically, for a 4-parallel 576-tap filter, the proposed design saves 144 multipliers (14.3%), 135 adders (10.2%) and 143 delay elements (11.1%).

High-speed long polynomial multiplication is important for applications in homomorphic encryption (HE) and lattice-based cryptosystems. This paper addresses low-latency hardware architectures for long polynomial modular multiplication using the number-theoretic transform (NTT) and inverse NTT (iNTT). Parallel NTT and iNTT architectures are proposed to reduce the number of clock cycles to process the polynomials. Chinese remainder theorem (CRT) is used to decompose the modulus into multiple smaller moduli. Our proposed architecture, namely PaReNTT, makes three novel contributions. First, cascaded parallel NTT and iNTT architectures are proposed such that any buffer requirement for permuting the product of the NTTs before it is input to the iNTT is eliminated. This is achieved by using different folding sets for the NTTs and iNTT. Second, a novel approach to expand the set of feasible special moduli is presented where the moduli can be expressed in terms of a few signed power-of-two terms. Third, novel architectures for pre-processing for computing residual polynomials using the CRT and post-processing for combining the residual polynomials are proposed. These architectures significantly reduce the area consumption of the pre-processing and post-processing steps. The proposed long modular polynomial multiplications are ideal for applications that require low latency and high sample rate such as in the cloud, as these feed-forward architectures can be pipelined at arbitrary levels. Pipelining and latency tradeoffs are also investigated. Compared to a prior design, the proposed architecture reduces latency by a factor of 49.2, and the area-time products (ATP) for the lookup table and DSP, ATP(LUT) and ATP(DSP), respectively, by 89.2% and 92.5%. Specifically, we show that for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n=4096$ </tex-math></inline-formula> and a 180-bit coefficient, the proposed 2-parallel architecture requires 6.3 Watts of power while operating at 240 MHz, with 6 moduli, each of length 30 bits, using Xilinx Virtex Ultrascale+ FPGA.

Fermat and Mersenne number-theoretic transforms (NTTs) are relatively easy to implement, but they are unsuitable for many DSP applications, due to small block length over wordlength. The authors present VLSI design techniques appropriate for a wider range of NTTs, including maximum-length NTTs, and outline a systolic architecture exploiting block-length factorization to decompose the architecture into submodules, themselves systolic NTTs. The design avoids the explicit implementation of modular addition, accumulation, and multiplication by using systolic basis converters, which inherently perform the tasks described. The implementation of a maximum-length 60pt NTT is described as an example. It uses binary to ternary basis conversion to perform all addition and multiplication, and ternary basis compression to perform accumulation. >

The efficient quantum circuit of Post Quantum Cryptography (PQC) impacts both performance and security because Grover’s algorithm, upon which various attacks are based, also requires a circuit. Therefore, the implementation of cryptographic operations in a quantum environment is considered to be one of the main concerns for PQC. Most lattice-based cryptography schemes employ Number Theoretic Transform (NTT). Moreover, NTT can be efficiently implemented using the modulus \(p=k\cdot 2^{m}+1\), called Proth number, and there is a need to elaborate on the quantum circuit for a modular multiplication over p. However, to the best of our knowledge, only quantum circuits for modular multiplication of the general odd modulus have been proposed, and quantum circuits for specific odd modulus are not presented. Thus, this paper addresses this issue and presents a new optimized quantum circuit for Proth Number Modular Multiplication (PNMM) which is faster than Rines et al.’s modular multiplication circuit. According to the evaluation with commonly used modulus parameters for lattice-based cryptography, our circuit requires an approximately 22%–45% less T-depth than that of Rines et al.’s.KeywordsCDKM adderProth numberQuantum circuitModuluar multiplicationLatticeNumber theoretic transform

Adaptive FIR filters are important in modern digital signal processing applications, and many situations require significant computational power attainable only through multi-processor configurations. Various block processing techniques have been proposed as viable alternatives to the sequential implementations to achieve the high throughput rate and reduce the effect of finite word length. While there are algorithm-based fault-tolerant techniques for protecting general digital signal processing systems against temporary/permanent failures, the specific features and requirements of the adaptive filtering systems have been largely ignored in the fault tolerance literature. By identifying common operations among different block adaptive filtering algorithms, however most operations of a particular algorithm can be protected with reasonably low-cost. We present a fine-grained approach, a highly efficient implementation of the well-known checksum encoding scheme, for protecting block adaptive filters. Through properly partitioning the input data, checksums for a parallel adaptive FIR filter can be calculated with reduced complexity. Computational and hardware overhead of the proposed scheme are analyzed, and shown to be proportional to the total number of partitioned submatrices.

Lattice-based post-quantum cryptography relies on fast polynomial multiplication. The Number-Theoretic Transform (NTT) is the key operation that enables this acceleration. To provide high throughput and low latency while keeping the area overhead small, hardware implementations of the NTT is essential. This is particularly true for resource-constrained devices. However, existing NTT accelerators either achieve high throughput at the cost of large area overhead or provide compact designs with limited pipelining and low operating frequency. Therefore, this article presents a compact, seven-stage pipelined NTT accelerator architecture for post-quantum cryptography, using the CRYSTALS–Kyber algorithm as a case study. The CRYSTALS–Kyber algorithm is selected due to its NIST standardization, strong security guarantees, and suitability for hardware acceleration. Specifically, a unified three-stage pipelined butterfly unit is designed using a single DSP48E1 block for the required integer multiplication. In contrast, the modular reduction stage is implemented using a four-stage pipelined, lookup-table (LUT)-only Barrett reduction unit. The term “LUT-only” refers strictly to the reduction logic and not to the butterfly multiplication. Furthermore, two dual-port BRAM18 blocks are used in a ping-pong manner to hold intermediate and final coefficients. In addition, a simple finite-state machine controller is implemented, which manages all forward NTT (FNTT) and inverse NTT (INTT) stages. For validation, the proposed design is realized on a Xilinx Artix-7 FPGA. It uses only 503 LUTs, 545 flip-flops, 1 DSP48E1 block, and 2 BRAM18 blocks. The complete FNTT and INTT with final rescaling require 1029 and 1285 clock cycles, respectively. At 200 MHz, these correspond to execution times of 5.14 µs for the FNTT and 6.42 µs for the INTT.

This paper presents design algorithms for hybrid filter banks (HFBs) for high-speed, high-resolution conversion between analog and digital signals. The HFB is an unconventional class of filter bank that employs both analog and digital filters. When used in conjunction with an array of slower speed converters, the HFB improves the speed and resolution of the conversion compared with the standard time-interleaved array conversion technique. The analog and digital filters in the HFB must be designed so that they adequately isolate the channels and do not introduce reconstruction errors that limit the resolution of the system. To design continuous-time analog filters for HFBs, a discrete-time-to-continuous-time ("Z-to-S") transform is developed to convert a perfect reconstruction (PR) discrete-time filter bank into a near-PR HFB; a computationally efficient algorithm based on the fast Fourier transform (FFT) is developed to design the digital filters for HFBs. A two-channel HFB is designed with sixth-order continuous-time analog filters and length 64 FIR digital filters that yield -86 dB average aliasing error. To design discrete-time analog filters (e.g., switched-capacitors or charge-coupled devices) for HFBs, a lossless factorization of a PR discrete-time filter bank is used so that the reconstruction error is not affected by filter coefficient quantization. A gain normalization technique is developed to maximize the dynamic range in the finite-precision implementation. A four-channel HFB is designed with 9-bit (integer) filter coefficients. With internal precision limited to the equivalent of 15 bits, the maximum aliasing error is -70 dB, and with the equivalent of 20 bits internal precision, maximum aliasing is -100 dB. The 9-bit filter coefficients degrade the stopband attenuation (compared with unquantized coefficients) by less than 3 dB.

Summary Numerical simulations of elastic wave propagations are the critical components for seismic imaging and inversion. Finite-difference schemes yield high efficiency but fail to ensure the accuracy of the high wavenumber components. The pseudo-spectral algorithm is accurate up to the Nyquist frequency, and it is efficient because of the high level optimization of the fast Fourier transform (FFT) algorithm. The calculation of derivatives in elastic wave propagation could employ the success of FFT optimization. A conventional spectral method consists of three procedures: a forward real to complex (R2C) FFT, a multiplication of the derivative term, such as a for first derivatives, and a complex to real (C2R) inverse FFT. For any even number, the R2C FFT is actually utilizing a half-sized C2C FFT, and then a further spectral manipulation is employed to obtain the spectrum. We propose an efficient scheme to calculate the derivatives for elastic wave propagation in which we apply a forward C2C FFT, and then multiply it with a set of coefficients, and finally a C2C inverse FFT is applied to complete the calculations. With such scheme, a 30% of efficiency has been achieved. In the end, we demonstrate the accuracy and efficiency on a seismic imaging project.

As the computation bottleneck in lattice-based cryptography (LBC), the polynomial multiplication based on number theoretic transform (NTT) has been continuously studied for flexible hardware implementations with high area-efficiency. This paper presents an area-efficient and configurable NTT-based polynomial multiplier (AC-PM) incorporating algorithmic and architectural level optimization techniques. For the core operation of polynomial multiplication, two low-complexity and fast modular multiplication algorithms are introduced with loose constraints of LBC-friendly primes. Based on the proposed algorithms, a reconfigurable processing element (RPE) is dedicatedly designed to execute all the operations in an NTT-based polynomial multiplication: NTT, inverse NTT (INTT), and coefficient-wise multiplication (CWM). The proposed AC-PM can be configured with different numbers of RPEs and supports various polynomial degrees without recompilation. Additionally, the dataflow complexity is greatly simplified. More importantly, to the best of our knowledge, the twiddle factors are reused, for the first time, to support both NTT and INTT with multiple polynomial degrees, which leads to increased flexibility of AC-PM with small overhead on hardware resource. FPGA implementation results demonstrate that the proposed AC-PM significantly outperforms the prior arts in both flexibility and area efficiency.

Modern deep convolutional neural networks (CNNs) suffer from high computational complexity due to excessive convolution operations. Recently, fast convolution algorithms such as fast Fourier transform (FFT) and Winograd transform have gained attention to address this problem. They reduce the number of multiplications required in the convolution operation by replacing it with element-wise multiplication in the transform domain. However, fast convolution-based CNN accelerators have three major concerns: expensive domain transform, large memory overhead, and limited flexibility in kernel size. In this paper, we present a novel CNN accelerator based on number theoretic transform (NTT), which overcomes the existing limitations. We propose the low-cost NTT and inverse-NTT converter that only use adders and shifters for on-chip domain transform, which solves the inflated bandwidth problem and enables more parallel computations in the accelerator. We also propose the accelerator architecture that includes multiple tile engines with the optimized data flow and mapping. Finally, we implement the proposed NTT-based CNN accelerator on the Xilinx Alveo U50 FPGA and evaluate it for popular deep CNN models. As a result, the proposed accelerator achieves 2859.5, 990.3, and 805.6 GOPS throughput for VGG-16, GoogLeNet, and Darknet-19, respectively. It outperforms the existing fast convolution-based CNN accelerators up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.6\times $ </tex-math></inline-formula> .

Interferometric instruments have the following serious weak points: (1) the necessity of doing a Fourier transform that involves a vast amount of calculation; (2) the lack of knowledge of suitable measuring conditions until the Fourier transform is finished; and (3) the spectral resolution of the conventional Fourier-based techniques is significantly affected by the sampling rate, data length, and noise in signal processing. In this paper, an enhanced spectrometer is proposed using the modified forward-backward linear prediction method (MFBLP) with a search algorithm. To document the advantage of the method presented, a computer simulation for multiple-wavenumber estimation is investigated. The MFBLP method is truly superior to the fast Fourier transform (FFT) method. In general, the spectral resolution using the FFT method is proportional to the data length. In this paper, however, it is shown that excellent results can also be obtained from only 60 sample points using the FFT method. Moreover, from experimental results, we also conclude that the sampling rate must be consistent with the condition 632<f/sub p//spl middot/t/spl middot/D<3164, where f/sub p/, represents the value of the pulse generator frequency in Hz, t the observation time, and D the decimation factor.