A multi-processor system for Prolog processing

The architecture of an all gallium arsenide (GaAs) vector signal processor based on parallel GaAs 32-bit microproccessors is described. The vector processor includes a vector memory of 1 megabytes, a parallel operand bus architecture with eight parallel processing elements, and a control/scalar processor. The processing elements consist of a reduced instruction set computer with four floating-point coprocessors and local memory. This architecture has been evaluated using several benchmark programs, includinig complex FFT, complex inner product, and sort-and-merge routine. The results of this study indicate that the vector processor can perform a 1024-point complex radix-4 FFT, using 32-bit floating-point arithmetic, in 112 microseconds (350) megaflops) while consuming approximately 550 watts of power in a volume of approximately 0.1 cubic foot.

This paper reports results of a study to determine and compare the effectiveness of various techniques aimed at reducing memory interference in multiprocessor multi memory systems. A simulation model of a multiprocessor, driven by address traces, is used for evaluation purposes. Two approaches to interference reduction are considered, being the reduction of overlapping memory requirements through various memory allocation methods, and the use of local memory to reduce the request rate to shared memory. Both private and cache memory are considered for this purpose.

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...

Computer systems are extensively being used in today’s era and the advancement in computer systems has led to the evolution of various technologies. As the efficiency of the computer systems is to be enhanced, the usage of cache memory becomes a must. The cache memory problems occur when multiprocessor systems are used. When multiple processors are processors share a common memory pool, the problem of cache coherence occurs. Cache coherence is a state in which the cache memories of the processors must stay in coherence with each other. The data should be updated in all the cache systems. Various protocols are used to ensure cache coherence. This study delineates the cache memory architecture, cache coherence, and the issues that arise due to non-consistent data in the cache of multiprocessor systems. Moreover, this study also delineates the protocols of the cache coherence and also describes in detail the MISE protocol. This study will provide an in-depth review of cache, cache coherence, and the issues associated with cache coherence along with the solution.

LAMP is an introspective analysis and processing framework for AADL. With LAMP, exploration, verification, transformation or any other processing rules are directly embedded inside the AADL model as annex subclauses. LAMP is based on the underlying LMP (Logic Model Processing) technology that itself leverages the Prolog language and a Prolog inference engine. This paper illustrates the use of LAMP by five practical use cases addressing some of the most important design issues in critical real-time software development.

Cache memories have proven their effectiveness in the von Neumann architecture when localities of reference govern the execution loci of programs. A pure dataflow program, in contrast, contains no locality of reference since the execution sequence is enforced only by the availability of arguments. Instruction locality may be enhanced if, dataflow programs are reordered. Enhancing the locality of data references in the dataflow architecture is a more challenging problem. In this paper we report our approaches to the design of instruction, data (operand) and I-Structure cache memories using the Explicit Token Store (ETS) model of dataflow systems. We will present the performance results obtained using various benchmark programs.

The recent advance in dataflow processing - to combine the dataflow paradigm with the control flow paradigm - has brought out many new challenging issues. This hybrid organization has made it possible to study familiar control flow concepts within the framework of the dataflow architecture. The concept of cache memory has proven its effectiveness in the von Neumann architecture due to the spatial and temporal localities which govern the organization of the conventional programming environment. A dataflow paradigm, does not imply to the locality. However, dataflow programs can be reordered to enhance the locality of instruction references. This can be achieved by careful partitioning of a dataflow program into vertical layers of data dependent instructions, and proper distribution and allocation of the recurrence portions of the dataflow program. Enhancing the locality of data references in flow architecture is a more challenging problem. This paper studies the design of instruction, data (operand) and I-Structure cache memories. The performance results obtained using various benchmark programs are presented and analyzed.

In this paper we discuss two parallel data-driven models together with their implementations on multiprocessor systems. The parallel models use a dynamic scheduling strategy, and are for a rule-based expert system. All the models are domain independent. To support the use of these models, a “rulebase compiler” has been built to translate a rule base in text format into the data structure needed by the system. The results indicate satisfactory speed up performance for a small number of processors (< 10) and a reasonably large number of rules.

Scientific software frequently demands high performance in order to execute complex models in acceptable time. A major means of obtaining high performance is via parallel execution on multi-processor systems. However, traditional methods of programming for parallel execution can lead to substantial code-tangling where the needs of the mathematical model crosscut with the concern of parallel execution.Aspect-Oriented Programming is an attractive technology for solving the problem of code-tangling in high performance parallel scientific software. The underlying mathematical model and the parallelism can be treated as separate concerns and programmed accordingly. Their elements of code can then be woven together to produce the final application. This paper investigates the extent to which AspectJ technology can be used to achieve the desired separation of concerns in programs from the Java Grande Forum benchmark suite, a set of test applications for evaluation of the performance of Java in the context of numerical computation. The paper analyses three different benchmark programs and classifies the degrees of difficulty in separating concerns within them in a form suitable for AspectJ. This leads to an assessment of the influence of the design of a numerical application on the ability of AspectJ to solve this kind of code-tangling problem. It is concluded that: (1) scientific software is rarely produced in true object-oriented style; and (2) the inherent loop structure of many scientific algorithms is incompatible with the join point philosophy of AspectJ.Since AspectJ cannot intercept the iterations of for-loops (which are at the heart of high-performance computing), various object-oriented models are proposed for describing (embarrassingly parallel) rectangular double-nested forloops that make it possible to use AspectJ for encapsulating parallelisation in an aspect. Finally, a test-case using these models is presented, together with performance results obtained on various Java Virtual Machines.

A tightly coupled multiprocessor system where each processor has direct access to a shared memory is studied. The system used for the experiments has only eight processors, but it supports the concurrent fetch and add operation, which is used extensively in the graph-reducer. A parallel graph-reduction technique is developed for such a system, and the measurement of its performance is made via some benchmark programs. As a byproduct, a new on-the-fly garbage collector which combines two different collection techniques has been developed. A new read-only graph-traversal technique for any number of concurrent processes independently traversing a shared graph has also been developed. >

Large-scale MIN-based shared-memory multiprocessor systems have long shared memory latency. Private caches can improve memory access latency but they may suf fer from the cache coherence problem and potentially lower data locality due to data sharing and multiproces sor scheduling. These two problems also increase shared memory load and may result in frequent memory stalls. In this paper, we evaluate the performance of memory caches, a cache memory placed in front of shared memory, in a large-scale multiprocessor system in the presence of pro cessor caches. The memory cache is shown to have good performance and scalability.

The VL86C020 is a second-generation reduced-instruction-set-computer (RISC) processor that is upwardly software compatible with the VL86C010. The latest family member incorporates a 4-kB on-chip cache memory to increase performance and lower memory bandwidth demands. Since multiprocessor systems are now feasible, a new semaphore instruction has been added to assist in shared resource allocation. In this case study the development of this family of RISC devices from concept to implementation is examined. By offering the CPU and cache memory on a single device, and itself as a core, the processor offers a superior upward migration path because the highest frequency memory path is not required to cross a chip boundary. As process rules continue to shrink, the clock frequency can be increased for on-chip operations accordingly without undue demands on the external memory system bandwidth. >

The rationale for selecting the engineering field test site and the building cooling requirements are described. Descriptions of the Phase I activities are presented and descriptions of the overall cooling system and its major subsystems and components are provided. The preliminary design analyses conducted to select collector/storage, chiller module and thermal distribution components; operating features and estimated system performance are included. Economic analyses and the results obtained are described including an assessment of the commercialization potential for the solar cooling system. Phase II activities are presented and detailed design, construction and installation features of the solar system at the test site are described. Testing documentation is provided by the checkout and acceptance tests and their results are described.

The scan-100 collision Avoidance System (CAS) has been designed to assist in the avoidance of collision at sea by automating the radar plotting functions in a small digital computer linked to the ship's radar. A clear and easily understandable display is provided to present numerical data and computer-generated plots to the ship's officer for evaluation of the radar data and for planning a safe and timely action to avoid collisions. This paper discusses the system design philosophy as implemented and tested in an engineering prototype of the SCAN-100 CAS. This philosophy utilizes an integrated man-machine concept which employs the best capabilities of each. The routine functions of radar tracking and plotting are performed by the system, which then presents the information to the operator in the form of displays combining graphic plots and numerical data. Automatic alarms are provided by the computer, one based on closest-point-of-approach (CPA) and another based on target arrival at a guard-ring distance. A vital requirement for the effective operation of such a radar-based system is the processing of radar data prior to tracking. In particular, the system must distinguish between receiver noise, sea clutter, and valid targets. The SCAN-100 uses a radar preprocessor, especially designed for this purpose, as well as computer processing to achieve the necessary radar signal enhancement. Several aspects of this processing technique are discussed in the paper. The system has recently undergone testing. Results of these tests are also described.

Aurora is a prototype or-parallel implementation of the full Prolog language for shared-memory multiprocessors, developed as part of an informal research collaboration known as the “Gigalips Project”. It currently runs on Sequent and Encore machines. It has been constructed by adapting Sicstus Prolog, a fast, portable, sequential Prolog system. The techniques for constructing a portable multiprocessor version follow those pioneered in a predecessor system, ANL-WAM. The SRI model was adopted as the means to extend the Sicstus Prolog engine for or-parallel operation. We describe the design and main implementation features of the current Aurora system, and present some experimental results. For a range of benchmarks, Aurora on a 20-processor Sequent Symmetry is 4 to 7 times faster than Quintus Prolog on a Sun 3/75. Good performance is also reported on some large-scale Prolog applications.