Reduction of memory interference in multiprocessor systems

In multi-core systems, main memory is a major shared resource among processor cores. A task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared main memory system. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to reduce this interference and provide an upper bound on the worst-case interference on a multi-core platform that uses a commercial-off-the-shelf (COTS) DRAM system. We explicitly model the major resources in the DRAM system, including banks, buses, and the memory controller. By considering their timing characteristics, we analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel. We find that memory interference can be significantly reduced by (i) partitioning DRAM banks, and (ii) co-locating memory-intensive tasks on the same processing core. Based on these observations, we develop a memory interference-aware task allocation algorithm for reducing memory interference. We evaluate our approach on a COTS-based multi-core platform running Linux/RK. Experimental results show that the predictions made by our approach are close to the measured worst-case interference under workloads with both high and low memory contention. In addition, our memory interference-aware task allocation algorithm provides a significant improvement in task schedulability over previous work, with as much as 96 % more tasksets being schedulable.

Computer systems are extensively being used in today’s era and the advancement in computer systems has led to the evolution of various technologies. As the efficiency of the computer systems is to be enhanced, the usage of cache memory becomes a must. The cache memory problems occur when multiprocessor systems are used. When multiple processors are processors share a common memory pool, the problem of cache coherence occurs. Cache coherence is a state in which the cache memories of the processors must stay in coherence with each other. The data should be updated in all the cache systems. Various protocols are used to ensure cache coherence. This study delineates the cache memory architecture, cache coherence, and the issues that arise due to non-consistent data in the cache of multiprocessor systems. Moreover, this study also delineates the protocols of the cache coherence and also describes in detail the MISE protocol. This study will provide an in-depth review of cache, cache coherence, and the issues associated with cache coherence along with the solution.

A RISC-based multiprocessor system called MIEP (Multiple Inference Engine for Prolog) is proposed as a tool to construct an intelligent workstation for AI applications. The MIEP contains general purpose processor modules (processor with local memory) and PIER (a Prolog inference engine on a RISC) modules interconnected by a bus. A PIER module contains a LISCP (limited instruction set computer for Prolog) as the kernel Prolog processor, a floating point coprocessor, FPC, and a cache memory. The PIER module has been simulated and evaluated with some benchmark programs. Primary results show that PIER can achieve a peak performance of more than 500 KLIPS. In addition, a parallel execution model for Prolog on MIEP has been studied and evaluated. Design issues and features of the MIEP system are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Large-scale MIN-based shared-memory multiprocessor systems have long shared memory latency. Private caches can improve memory access latency but they may suf fer from the cache coherence problem and potentially lower data locality due to data sharing and multiproces sor scheduling. These two problems also increase shared memory load and may result in frequent memory stalls. In this paper, we evaluate the performance of memory caches, a cache memory placed in front of shared memory, in a large-scale multiprocessor system in the presence of pro cessor caches. The memory cache is shown to have good performance and scalability.

The VL86C020 is a second-generation reduced-instruction-set-computer (RISC) processor that is upwardly software compatible with the VL86C010. The latest family member incorporates a 4-kB on-chip cache memory to increase performance and lower memory bandwidth demands. Since multiprocessor systems are now feasible, a new semaphore instruction has been added to assist in shared resource allocation. In this case study the development of this family of RISC devices from concept to implementation is examined. By offering the CPU and cache memory on a single device, and itself as a core, the processor offers a superior upward migration path because the highest frequency memory path is not required to cross a chip boundary. As process rules continue to shrink, the clock frequency can be increased for on-chip operations accordingly without undue demands on the external memory system bandwidth. >

The concept of cache memory partitioning is handled and implemented few times earlier. Partitioning is essential in cache memory to attain still higher speed while searching and transaction of data, as L1 cache is comparatively small in size, memory interference in L1 cache is very low data, and instruction were partitioned easily. For effective use of multicore processor, cache partitioning or cache sharing is important. However, there are some limitations identified from many studies, like increase in simulation time, because of inter thread memory interfering, and inaccuracies in simulation. This paper explains a cache partitioning method for multicore systems using miss rate estimation. It reduces the interference of cache among concurrently executing process threads. The cache partitioning algorithm, using our novel approach, calculates the miss rate characteristics of individual threads at the run time, then dynamically partitions and distributes the cache memory among the threads, which are running concurrently, and thus improves the performance of multicore systems. The paper is divided into several sections; first, it explains all the basics related to the domain; secondly, it gives the details about all the papers which have been referred with a comparison. Finally, it focuses on future scope.

An approximate analytic tool called equilibrium point analysis is applied to the problem of memory interference in multiprocessor systems. It is a simple and powerful analytic tool based on the fluid approximation and has been widely used for packet broadcast systems. It is shown that quite general multiprocessor systems can be studied quite simply with this technique, these systems include those made up of many classes of processors and memory modules with arbitrary static memory reference patterns, and systems with bus connections between processors and memories. In most cases, the approximation is shown to be sufficiently good. One of the advantages of this technique is that the error is smaller for larger systems for which no appropriate analytic tools have existed until now.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Language models (LMs) are an essential element in statistical approaches to natural language processing for tasks such as speech recognition and machine translation (MT). The advent of big data leads to the availability of massive amounts of data to build LMs, and in fact, for the most prominent languages, using current techniques and hardware, it is not feasible to train LMs with all the data available nowadays. At the same time, it has been shown that the more data is used for a LM the better the performance, e.g. for MT, without any indication yet of reaching a plateau. This paper presents CloudLM, an open-source cloud-based LM intended for MT, which allows to query distributed LMs. CloudLM relies on Apache Solr and provides the functionality of state-of-the-art language modelling (it builds upon KenLM), while allowing to query massive LMs (as the use of local memory is drastically reduced), at the expense of slower decoding speed.

We propose a new, completely iterative traversal algorithm for ray tracing bounding volume hierarchies that is based on storing a parent pointer with each node, and on using simple state logic to infer which node to traverse next. Though our traversal algorithm does re-visit internal nodes, it intersects each visited node only once, and in general performs exactly the same ray-box tests and ray-primitive intersection tests---and in exactly the same order---as a traditional stack-based variant. The proposed algorithm can be used for computer architectures that need to minimize the use of local memory for processing rays or those that need to minimize the data transport such as distributed multi-CPU architectures.

Increasingly, multi-core architectures are proposed and multiprocessor systems are also realized within the FPGA. The communication mechanisms among devices are fundamental and influence the feasibility and performance of the system. The main ones can be based on the bus, on shared memory, or on NoC. The preferred communication, for versatility and ease of programming, is via a shared memory, which, in fact, you want to imitate in different ways. But a true multiport memory that allows simultaneous access to the same locations, has various manufacturing difficulties. In this contribution, the method that we use, to make the shared memory feasible and practically usable, is a targeted configuration of its structure. With a parameterization in FPGA of memory we want to adapt the architecture of communication to the communication needs of the multiprocessor system. So the idea is to try to reduce the required interconnections to share the memory locations among all processors, limiting them strictly to the operational needs of the application. We show the results achieved with implementations in FPGA comparing the occupation of the area and the required resources, trying to figure out if this, which happens to be an even non-trodden path, can lead to viable solutions to current and future needs of multiprocessor communication.

Modern embedded systems are typically integrated as multiprocessor system on chips, and are often characterized by the complex behaviors and dependencies that system components exhibit. Different events that trigger such systems normally cause different execution demands, depending on their event type as well as on the task they are processed by, leading to complex workload correlations. For example in data processing systems, the size of an events payload data will typically determine its execution demand on most or all system components, leading to highly correlated workloads. Performance analysis of such complex system is often very difficult, and conventional analysis methods have no means to capture the possible existence of workload correlations. This leads to overly pessimistic analysis results, and thus to too expensive system designs with considerable performance reserves. We propose an abstract model to characterize and capture workload correlations present in a system architecture, and we show how the captured additional system information can be incorporated into an existing framework for modular performance analysis of embedded systems. We also present a method to analytically obtain the proposed abstract workload correlation model from a typical system specification. The applicability of our approach and its advantages over conventional performance analysis methods is shown in a detailed case study of a multiprocessor system on chip, where the analysis results obtained with our approach are considerably improved compared to the results obtained with conventional analysis methods.

This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds under performance constraints. The cache memory stores the data from the disks for reuse. Enlarging the cache memory reduces disk accesses and disk utilization. This allows the disks to reduce their speeds and conserve energy because the disks' power consumption is quadratic to their speeds. However, the cache memory itself consumes power to retain data. Shrinking cache memory can save memory power while increasing disk accesses and degrading performance. Choosing proper cache sizes and rotation speeds can reduce the energy consumption of both memory and disks with satisfactory performance. We model cache resizing and speed setting as an optimization problem with minimizing the power consumption as objective and limiting disk utilization as constraints. We compare our method with the methods resizing cache based on request rates. The simulation results show that our method achieves better energy savings while limiting disk access latency.

URL matching is used in many network applications, including URL blacklisting, URL-based forwarding and URL shortening services. These applications need fast URL queries and updates, thus requiring an efficient updateable data structure. As the processing power of general-purpose multi-core processors increases, software-based approaches are better able to meet the speed requirements of URL matching. In this paper, we present our preliminary performance study of finite-automata- and hash-based URL matching implementations on commodity PCs. The impacts of the cache and memory allocation methods are discussed.

The potential of multiprocessor systems is often not fully realized by their system services. Certain synchronization methods, such as lock-based ones, may limit the parallelism. It is significant to see the impact of wait/lock-free synchronization design in key services for multiprocessor systems, such as the memory allocation service. Efficient, scalable memory allocators for multithreaded applications on multiprocessors is a significant goal of recent research projects.We propose a lock-free memory allocator, to enhance the parallelism in the system. Its architecture is inspired by Hoard, a successful concurrent memory allocator, with a modular, scalable design that preserves scalability and helps avoiding false-sharing and heap blowup. Within our e.ort on designing appropriate lock-free algorithms to construct this system, we propose a new non-blocking data structure called flat-sets, supporting conventional “internal” operations as well as “inter-object” operations, for moving items between flat-sets.We implemented the memory allocator in a set of multiprocessor systems (UMA Sun Enterprise 450 and ccNUMA Origin 3800) and studied its behaviour. The results show that the good properties of Hoard w.r.t. false-sharing and heap-blowup are preserved, while the scalability properties are enhanced even further with the help of lock-free synchronization.KeywordsMultiprocessor SystemShared LocationMove OperationMemory RequestFalse SharingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper presents the design and implementation of a shared memory system to reduce memory interference in an environment of a multi-processor system composed of a pool of EVAL-11 processors and aiming for high performance through parallel evaluation of a Lisp program.The performance of a multi-processor system varies with many factors. We introduced several useful methods to control the granularity of the processes, and have confirmed their effect through dynamic measurement on the multi-processor Lisp machine — the EVLIS machine —. Dynamic measurement also shows that the interference of access to shared memory is a difficult problem. We show a solution for this problem in two different ways. First, we modified the form of the free cell list to reduce the interference from exclusive operation. Second, we present the design of the shared memory system which solves the memory interference on read accesses in particular, and its implementation with the use of conventional memory chips and TTL's.