Equilibrium point analysis of memory interference in multiprocessor systems

A novel design for an M-user B-server arbiter for a multiple bus system is presented. The arbitration circuit maintains fairness when it is used in a low-order interleaved memory system. The arbiter is also fair for a general-purpose multiprocessor system where the memory modules are uniformly accessed by the processors. The arbitration time grows at a rate O(log/sub 2/ M), where M is the number of memory modules in a system. When a system has more than four memory modules, both the gate count and delay of the present design are less than those of previous designs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents quadratic programming models of memory conflict in multiprocessor systems where main memory consists of a set of memory modules common to all processors. Two jobs (programs) are said to be in conflict, or subject to memory conflict, whenever at a given time portions of them must be executed in the same memory module by different processors. We are interested in minimizing the total conflict by the proper assignment of jobs to main memory. Two allocation models are considered: one in which the jobs-to-memory assignment is to be made independent of any particular processors-to-jobs schedule, that is, expected memory conflict is to be minimized over the space of all schedules; and the second in which a definite processor schedule is assumed to be available. For both models, algorithms are formulated for the assignment of jobs to memory.

We present a discrete Markov chain model for analyzing the effect of memory interference in processor-memory interconnections of buffered multiprocessor systems. Each module is assumed to be one of the following three types-hot memory, favorite memory and memory which is neither hot nor favorite. The analytical solutions are restricted to 2/spl times/M and N/spl times/2 systems, where N and M are respectively the number of processors and memory modules. The general case is analyzed using simulation studies and compared with the analytic results. In all cases the main criterion of the system performance are the effective bandwidth, mean queue length and mean waiting time for a memory request. It is expected that increasing the number K of hot modules will improve the performance. We also estimate the asymptotic bandwidth and propose a heuristic to find an upper bound on K beyond which the bandwidth saturates.

PurposeThe purpose of this paper is to present a method to calculate the transient induced voltages along the underground pipelines and analyze the transient interference generated in the pipelines due to the inductive coupling in the fault‐to‐ground condition of power lines in close proximity.Design/methodology/approachBased on finite difference‐time domain method, an improved method is proposed to calculate transient inductive interference in underground metallic pipelines due to a fault in nearby power lines. The frequency‐dependent problem in the analysis of transient interference is solved in phase domain. Compared with the traditional method, the disposal of phase‐modal transformation matrices’ frequency‐dependent characteristic is avoided and the calculation is simplified by using vector fitting approach and recursive algorithm greatly in the proposed method.FindingsA novel improved method is proposed to calculate transient induced voltage distribution along underground metallic pipelines due to a fault in nearby power lines. Results show that the peak value of transient induced voltage at the most critical point is about 1.15 times of the magnitude in the steady state without the fault removed and the analysis of transient inductive interference is necessary in the fault‐to‐ground case of power lines.Practical implicationsIn order to mitigate the interference from power lines to nearby pipelines, pipelines should be good grounded and positioned as far away from the power line as possible. In high soil resistivity areas, the common corridor should be avoided.Originality/valueThe paper presents a method to calculate the transient induced voltages along the underground pipelines and analyze the transient interference generated in the pipelines due to the inductive coupling in the fault‐to‐ground condition of nearby power lines. The proposed method is general and can also be applied to other transient interference studies such as crosstalk problems of communication networks and interference between power lines and aboveground pipelines or communication cables. Effects of various parameters upon the inductive interference generated in underground pipelines due to a fault in nearby power lines are analyzed to be a guide for controlling the inductive interference.

A. INTRODUCTION In 2010 a raft of articles offered contrasting views on analytic tools for assessing unilateral effects from differentiated products mergers. They provided some useful insights but did not acknowledge that this is just one of many scenarios encountered in merger assessment, and they paid insufficient attention to the problems faced by a competition agency. We revisit this debate to clarify the issues and place them in context. We first review the basics of unilateral merger effects, the model-based analytic tools used for assessing unilateral effects, and the contrasting views expressed in the recent debate. With this foundation, we consider the choice among analytic tools at three stages of a merger assessment—initial screening, ultimate decision, and courtroom presentation. We explain how the proper analytical tool for a particular merger depends on the information available. We also explain how the proper analytic tool for a particular merger depends on the competitive process in which the merging firms engage and how the merger is apt to affect it. Our experience has been that shortrun price competition among differentiated products most often is not a satisfactory characterization of the process, and we offer two scenarios that require tools very different than those applicable to differentiated consumer products. In addition, we address the Upward Pricing Pressure Index (UPPI), which was a focal point in the recent debate. We find some merit in the idea of a very simple tool for differentiated products mergers and suggest a slightly simpler calculation. We also conclude that either as a screen or as part of a full assessment of a merger, other tools are preferable to the UPPI.

Aiming at the problem of co-frequency interference between non-geostationary orbit (NGSO) constellation system and geostationary orbit (GSO) satellite system, aggregated interference analysis model for NGSO multi-beam constellation system is established, and the dual step algorithm of spatial position probability is proposed for interference analysis simulation based on relevant ITU recommendations and reports. This method discretizes the spatial position of NGSO reference satellite by dividing the latitude and longitude grid. Then the probability density function of interference-to-noise ratio (I/N) can be obtained. Taking OneWeb and SINOSAT-5 system as the typical NGSO constellation system and GSO satellite system respectively, the interference analysis is performed by using the proposed method, and the results are verified with International common tool. The results illustrate that when the threshold of the number of NGSO satellites whose separation angle is not more than the included angle of the fine step size region is 20%, both the result accuracy and calculation efficiency can be balanced. The I/N distribution is related to the latitude of the ground station.

Modern computer systems employ multiple cores and various layers of memory modules such as local memory and remote memory. Cores and memory modules are connected through diverse micro-architecture resources including LLC (Last Level Cache), IMC (Integrated Memory Controller), Interconnect, and GQ (Global Queue). Since these micro-architecture resources are shared among cores while accessing data, the interference of these resources gives a significant influence on the system performance. To explore this influence, in this paper, we observe how the execution time changes when we execute SPEC CPU2006 and PARSEC benchmarks with different data and threads placement on our experimental system. We also measure the usage behavior of the micro-architecture resources using PMU (Performance Monitoring Unit) and analyze the correlation between the execution time and PMU parameters. Our finding is that the two PMU parameters, called IMC_reads and writes and QHL_requests are good indicators whose differences are well matched with the performance differences. It implies that changing these indicators in a positive way by controlling data and/or thread placement can boost the system performance.

One of the difficulties in calculating the capacity of certain Poisson channels is that <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> (¿), the entropy of the Poisson distribution with mean <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">¿</i> , is not available in a simple form. In this paper, we derive upper and lower bounds for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> (¿) that are asymptotically tight and easy to compute. The derivation of such bounds involves only simple probabilistic and analytic tools. This complements the asymptotic expansions of Knessl (1998), Jacquet and Szpankowski (1999), and Flajolet (1999). The same method yields tight bounds on the relative entropy <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> ) between a binomial and a Poisson, thus refining the work of Harremoe¿s and Ruzankin (2004). Bounds on the entropy of the binomial also follow easily.

BACKGROUNDDetermining the cause of a pleural effusion is greatly facilitated by analysis of the pleural fluid.Many pleural effusions remain undiagnosed after routine tests of pleural fluid.So, we need a simple and safe investigative tool to evaluate such undiagnosed pleural effusions. MATERIALS AND METHODSPatients with undiagnosed exudative pleural effusion after pleural fluid analysis were subjected to pleural biopsy using Abram's pleural biopsy needle under local anaesthesia and the specimen was sent, histopathological examination, reverse transcriptase polymerase chain reaction for tuberculosis and culture for tuberculosis by BACTEC. RESULTSAbout 78.5% of cases were diagnosed when combining histopathological examination, BACTEC culture and reverse transcriptase polymerase chain reaction on pleural biopsy specimen. CONCLUSIONClosed pleural biopsy can be used as an easy, quick, cost effective and relatively safe method to diagnose an exudative effusion not diagnosed by pleural fluid analysis.Combination of histopathological examination, BACTEC culture and reverse transcriptase polymerase chain reaction in closed pleural biopsy has a greater diagnostic yield in diagnosing exudative effusions not diagnosed by pleural fluid analysis.

The transition towards multi-processor systems with shared resources is challenging for real-time systems, since resource interference between concurrent applications must be bounded using timing analysis. There are two common approaches to this problem: 1) Detailed analysis that models the particular resource and arbiter cycle-accurately to achieve tight bounds. 2) Using temporal abstractions, such as latency-rate (LR) servers, to enable unified analysis for different resources and arbiters using well-known timing analysis frameworks. However, the use of abstraction typically implies reducing the tightness of analysis that may result in over-dimensioned systems, although this pessimism has not been properly investigated. This paper compares the two approaches in terms of worst-case execution time (WCET) of applications sharing an SDRAM memory under Credit-Controlled Static-Priority (CCSP) arbitration. The three main contributions are: 1) A detailed interference analysis of the SDRAM memory and CCSP arbiter. 2) Based on the detailed analysis, two optimizations are proposed to the LR analysis that increase the tightness of its interference bounds. 3) An experimental comparison of the two approaches that quantifies their impact on the WCET of applications from the CHStone benchmark.

Technical Analysis: Does Recent Market Data Substantiate the Efficient Market Hypothesis?

In vector multiprocessor systems, collisions in the interconnection network and conflicts in the memory modules are the main causes of the performance degradation. In this work we use a synchronized interconnection network, and propose an interleaved storage scheme and an out-of-order access to the elements of the stream that allow conflict-free access. The streams are generated by the different processors in an asynchronous manner. The mechanism works for the most common strides found in real programs. The hardware required is also described and its complexity is shown to be equivalent to the complexity when the processor requests the elements in order.

This simulation-based study examines the behavior of a realistic shared-memory multiprocessor system that utilizes Omega networks. A unique aspect is the presence of bursts of requests, such as processors with associated vector units or caches would generate. It is demonstrated that the forward network, the memory modules, and the reverse network of such a system interact and affect each other’s performance such that good performance depends less on the speed of any one component than on the interaction between them. Cost-effective modifications for improving this balance are evaluated. Within the range of system sizes studied (32 to 512 processors), results show that MIN-based systems that operate close to their peak memory bandwidth can indeed be constructed.

The performance of a multiprocessor system greatly depends on the bandwidth of its memory architecture. In this paper, uniform memory architectures with various interconnection networks including crossbar, multiple-buses and generalized shuffle networks are studied. We propose a general method based on the Markov chain model by assuming that the blocked memory requests will be redistributed to the memory modules in the next memory cycle. This assumption results in an analysis with lower complexity where the number of states is linearly proportional to the number of processors. Moreover, it can provide excellent estimation on the system power and memory bandwidth for all three types of interconnection networks as compared with the simulation results in which the blocked memory requests are resubmitted to the same memory module. Comparisons also show that our method is more general and precise than most existing analysis methods. The method is further extended to estimate the performance of multiprocessor system with caches. The approximation results are also shown to be remarkably good.

An analytical performance model for multistage interconnection networks with finite, infinite and zero length buffers