A Multiplier Structure Based on a Novel Real-time CSD Recoding

Auscultation, the technique of listening to heart sounds, remains a primary detection tool for diagnosing heart valve disorders. Other techniques, e.g. electrocardiography, ultrasound, etc, are accurate as well as informative; but expensive. With major advancement in the speed of computers, heart sound signals can be processed with ease by memory efficient digital signal processing and pattern recognition algorithms. This paper presents a digital signal processor (DSP) implementation of such a technique by using new threshold criteria. The proposed work can detect whether a heart sound recording belongs to a person suffering from valvular heart disease or not by giving ‘diseased’ or ‘not diseased’ decisions. The algorithm is tested for nine commonly occurring pathological problems and normal heart sound. The robustness of the algorithm is also checked against synthetically injected additive white Gaussian noise (AWGN) with different SNR levels. It is found to give an accuracy of 96.67% up to SNR values of 15 dB and 93.33% up to SNR values of 5 dB.

The role of software is becoming increasingly important in the implementation of digital signal processing (DSP) applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state of the art in programming language and compiler technology for DSP software implementation. In particular, we review techniques for high-level block-diagram-based modeling of DSP applications; the translation of block-diagram specifications into efficient C programs using global target-independent optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors using architecture-specific and retargetable back-end optimizations. We also point out important directions for further investigation.

We introduce and describe the initial evaluation of a new low-cost augmented violin prototype, with research focused on the user experience when playing such hybrid physical-digital instruments, and the exploration of novel interactive performance techniques. Another goal of this work is wider platform accessibility for players, via a simple `do-it-yourself' approach described by the design herein. While the hardware and software elements are open source, the build process can nonetheless require non-insignificant investments of time and money, as well as basic electronics construction skills. These have been kept to a minimum wherever possible. Our initial prototype is based upon an inexpensive electric violin that is widely available online for approximately $200 USD. This serves as the starting point for construction, to which the design adds local Digital Signal Processing (DSP), gestural sensing, and sound output. Real-time DSP algorithms are running on a mobile device, which also incorporates orientation/gesture sensors for parameter mapping, with the resulting sound amplified and rendered via small loudspeakers mounted on the instrument. The platform combines all necessary elements for digitally-mediated interactive performance; the need for a traditional computer only arises when developing new DSP algorithms for the platform. An initial exploratory evaluation with users is presented, in which performers explore different possibilities with the proposed platform (various DSP implementations, mapping schemes, physical setups, etc.) in order to better establish the needs of the performing artist. Based on these results, future work is outlined leading towards the development of a complete quartet of instruments.

The issues related to the study of the possibilities of mathematical and software modeling of digital algorithms for discrete Fourier transform without algorithmic multiplication operations are considered. The relevance of the study is due to the need to reduce the computational complexity of digital signal processing algorithms. The purpose of the study is to formalize a numerical method for the multi–stage discrete Fourier transform of a digital complex signal. The methods of mathematical and software modeling of numerical methods of digital signal processing were used in the study. The results of the study showed and confirmed the possibility of modeling a numerical method of multi-stage discrete Fourier transform of a digital complex signal based on numerical methods of difference digital filtering with integer difference coefficients of various orders of difference and a numerical method of reducing direct calculations of complex functions to perform simple operations of addition and shift. The concept of a multi-stage discrete Fourier transform and the concept of this transformation are defined and described. Its mathematical model is proposed and the numerical method of such transformation is formalized. It is noted that it allows to reduce the computational complexity of the hardware and software implementation of digital signal processing through the use of numerical methods of differential digital filtering, directed enumeration and comparative analysis of acceptable sets of numerical values of integer coefficients, which provides the possibility of reducing the error of the numerical method of multi-stage discrete Fourier transform. To reduce the computational complexity of his algorithms for isolating the harmonic components of a digital complex signal, the principles of dividing its frequency spectrum into narrow-band spectral components, frequency shifting of these components and their low-frequency difference digital filtering without performing arithmetic multiplication operations are applied.

The real-time implementation of many digital signal processing (DSP) algorithms requires novel algorithm mapping methods and architectures. Some of the architectures developed thus far include data-flow systems, systolic arrays, and wavefront arrays. Ideas from these architectures are combined with the concept of block data flow processing to present the block data flow architecture (BDFA). Key features of the BDFA include direct input/output to all processors, linear data-flow, and globally asynchronous operation. Use of the BDFA for 2-D filtering is presented and analyzed. The analysis is facilitated using timing results generated by a simulator developed with the C programming language. Development of the simulator is discussed in terms of how an architecture like the BDFA can be described and simulated in C. Simulation results show that the increase in throughput with the number of processors is nearly linear. >

The data-flow graph (DFG) is an important graph-theoretic model for multiprocessor implementation of real-time digital signal processing (DSP) algorithms. Given a time schedule for a DFG, we consider the problem of the processor-optimal assignment for a fully static schedule. Previously, the solution of this problem was found by solving an integer programming problem. We propose a linear programming approach to solving the problem.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

The canonic sign digit (CSD) number system is both a technique for representing fixed-point numbers and an algorithm for multiplying one fixed-point number by another. Through the addition of look-up-table (LUT) based control logic, the simple CSD scaler (ie: fixed-coefficient multiplier) can be converted to a hardware-efficient full four-quadrant multiplier with applications in adaptive filters, digital up-converters and down-converters, Two novel circuits are designed to take advantage of the Xilinx FPGA architecture to provide simple, yet hardware-efficient multipliers. The multipliers are designed for application in adaptive digital filters, Fourier transforms, and other DSP applications that require an efficient four-quadrant multiplier.

The present work describes some of the research effort on Active Noise Control (ANC) being jointly developed by the Catholic University of Minas Gerais (PUC-MINAS) and the Federal University of Minas Gerais (UFMG). Considerations about the implementation of Digital Signal Processing for noise control in ducts has been presented. The objective is to establish a study on Active Noise Control in ducts combining geometry and acoustic parameters modification together with adaptive digital filtering implementation. Both algorithm and digital signal processing details are also discussed. The main results for a typical application where real attenuation has been obtained are presented and considered according to their use in developing real applications. The authors also believe that the present text should provide an interesting overview for both designers and students concerned about Active Noise Control in ducts. (To be presented in Portuguese.)

This paper proposes a practical query-by-singing/humming (QbSH) system that retrieves polyphonic music such as an MP3 and its commercial applications. The performance of music retrieval system is mainly affected by the server. This paper discusses developing the state-of-the-art server side software stack which has several managers and plug-in engines. It also describes implementation of digital signal processor (DSP) module for stand-alone embedded platforms. The paper shows three different models for its commercial applications like smart phone, laptop and karaoke. We evaluate the performance of the proposed system with polyphonic music datasets using users' humming datasets as the input query.

McDAS, a software environment designed to support the real-time implementation of digital signal processing (DSP) applications onto multiple processors, is described. Users program their algorithms as they would on a single processor, and McDAS automatically schedules and compiles the program onto the target multiprocessor. The scheduler maximizes the computational throughput by simultaneously considering pipelining, retiming, and parallelism while accounting for processor and memory constraints, as well as interprocessor communication delays. If the architecture is scalable or configurable, the scheduler can be invoked with different numbers of processors and multiprocessor topologies to explore various implementations. The code generator is similarly retargetable to different memory architectures and core processors. Data buffers and synchronizations are automatically inserted to ensure correct execution. The code generated can also execute the algorithms with either quasi-infinite precision or bit-true precision, allowing the algorithm designer to assess the effects of quantization and truncation. The results on a set of benchmarks are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The design and analysis of software which implements digital signal processing (DSP) algorithms on multiprocessor systems is examined. The DSP algorithms that are considered exhibit certain characteristics which are common of DSP algorithms used in communication and control systems. The analysis methods developed use linear complexity algorithms to analyze the software that implements the DSP algorithms. The first step involves finding the repeat factors associated with a basic cycle of the algorithm. Using these repeat factors it is straightforward to (1) find the precedence relationships between tasks and finally a feasible schedule for the multiprocessor, and (2) coordinate and organize the efforts to optimize the software. >

The camera digital signal processing (DSP) core is a key component for a video catching system. In this study, first high-performance and low-complexity algorithms are developed for the camera DSP system. The main functions involve the color interpolation, white balance, color space transformation, auto gain control, edge enhancement and color enhancement. Simulations demonstrate that the proposed method can achieve good quality as for a color-filter-array format camera. Based on the algorithms, the DSP processor is developed with pipelined structure. The prototyping chip is verified with one FPGA device, and then its ASIC is also realized with 0.35um CMOS process. A real-time camera system with 1270×792 resolutions is successfully demonstrated by the combination with the extra components within one PCB broad.

Droop control is a common control strategy used in DC microgrids to manage power distribution among parallel Distributed Energy Resource (DER) converters. With droop control, the static dc bus voltage varies in a specified range according to load conditions. In order to maintain the dynamic dc bus voltage in the same range during load changes, droop-controlled DER converters usually have either large output capacitance or high voltage loop bandwidth. The latter enables the adoption of small output capacitance that improves the dc bus behaviour also during bus faults. However, with traditional control techniques, for example, the single-sampled PID controllers, the voltage loop bandwidth is limited by the control delay, including the computation time and the modulation delay. From this point of view, oversampled hysteresis control is appealing, because it reduces the modulation delay by removing the modulator. Also, the hysteretic nature allows nonlinear switching actions during transient, which further speeds up the dynamic response. Consequently, small output capacitance can be used without concerns of overvoltage and undervoltage. Moreover, hysteresis control is typically implemented on Field Programmable Gate Arrays (FPGAs). Differently, this paper focuses on the less-expensive Digital Signal Processors (DSPs) implementation. The influence of additional computation time introduced by DSP on the converter's stability is also analyzed. Simulations and experiments are carried out to verify the performance of the DSP-implemented hysteresis droop controller.