Fully static processor-optimal assignment of data-flow graphs

Auscultation, the technique of listening to heart sounds, remains a primary detection tool for diagnosing heart valve disorders. Other techniques, e.g. electrocardiography, ultrasound, etc, are accurate as well as informative; but expensive. With major advancement in the speed of computers, heart sound signals can be processed with ease by memory efficient digital signal processing and pattern recognition algorithms. This paper presents a digital signal processor (DSP) implementation of such a technique by using new threshold criteria. The proposed work can detect whether a heart sound recording belongs to a person suffering from valvular heart disease or not by giving ‘diseased’ or ‘not diseased’ decisions. The algorithm is tested for nine commonly occurring pathological problems and normal heart sound. The robustness of the algorithm is also checked against synthetically injected additive white Gaussian noise (AWGN) with different SNR levels. It is found to give an accuracy of 96.67% up to SNR values of 15 dB and 93.33% up to SNR values of 5 dB.

The design and analysis of software which implements digital signal processing (DSP) algorithms on multiprocessor systems is examined. The DSP algorithms that are considered exhibit certain characteristics which are common of DSP algorithms used in communication and control systems. The analysis methods developed use linear complexity algorithms to analyze the software that implements the DSP algorithms. The first step involves finding the repeat factors associated with a basic cycle of the algorithm. Using these repeat factors it is straightforward to (1) find the precedence relationships between tasks and finally a feasible schedule for the multiprocessor, and (2) coordinate and organize the efforts to optimize the software. >

Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multiplications. In this paper, we introduce a novel multiplier structure that converts from 2's complement to canonical signed digit (CSD) representation in real time. The proposed algorithm increases the number of zero partial products (which can be simplified by shift operations) to approximately 66.7% compared with 50% for modified Booth's recoding. Also, the proposed hardware structure reduces the non-zero partial products to a minimum, and consequently the number of arithmetic operations in the carry-save structure is reduced. So, our proposed hardware decreases both the time required for multiplication and the power consumption of the multiplier. Furthermore, because the proposed structure uses real time CSD recoding, and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be used to implement digital filters with non-fixed filter coefficients, such as adaptive filters.

The real-time implementation of many digital signal processing (DSP) algorithms requires novel algorithm mapping methods and architectures. Some of the architectures developed thus far include data-flow systems, systolic arrays, and wavefront arrays. Ideas from these architectures are combined with the concept of block data flow processing to present the block data flow architecture (BDFA). Key features of the BDFA include direct input/output to all processors, linear data-flow, and globally asynchronous operation. Use of the BDFA for 2-D filtering is presented and analyzed. The analysis is facilitated using timing results generated by a simulator developed with the C programming language. Development of the simulator is discussed in terms of how an architecture like the BDFA can be described and simulated in C. Simulation results show that the increase in throughput with the number of processors is nearly linear. >

Traditional digital signal processing technology based on DSP and FPGA is more suitable for real-time signal processing, and is limited by data scale and frequency resolution, making it unsuitable for offline data processing, analysis and mining under large-scale data Application. At present, the industrial big data analysis platform can use Spark as a calculation engine for real-time signal processing and offline signal processing acceleration, but the analysis platform lacks mathematical calculation solutions such as digital signal processing suitable for distributed parallel calculation engines. This article is based on time the parity decomposition is selected, and the fast Fourier transform is realized by MATLAB software. Based on an example of the application of the compiled FFT source program, this article analyses the frequency spectrum of discrete-time and continuous-time signals of limited length.

This paper presents a newly developed laboratory paradigm for teaching applied or real-time digital signal processing courses. It involves the utilization of smartphones to implement digital signal processing algorithms in real-time using ARM processors of smartphones. Representative laboratory experiments together with an application project running on smartphones as apps are discussed in the paper. It is shown that such a paradigm provides a cost-free and a truly mobile laboratory environment for students to learn implementation aspects of signal processing algorithms.

In this article, we review our recent research progresses on the field programmable gate array (FPGA)-based real-time generation and reception of orthogonal frequency-division multiplexing (OFDM) signals for the short-reach direct-detection system and radio-over-fiber (RoF) system. With the low-complexity real-time digital signal processing (DSP) algorithms, a high-definition video signal with a data rate of 2.97 Gb/s transmission over 20 km single-mode fiber (SMF) without using forward error correction (FEC) technique is experimentally demonstrated in an intensity-modulated direct-detection optical OFDM system in the presence of sampling frequency offset (SFO). In addition, a real-time X-band OFDM-RoF system with heterodyne detection was also realized. With the help of Reed-Solomon coding with a multiplesymbol interleaving/de-interleaving scheme, the 16-ary quadrature amplitude modulation (16-QAM) OFDM-RoF signals over 10-m wireless and 2.26-km SMF-28 link was successfully achieved with a post-FEC bit error rate less than 1×10-9.

Validation of Peripheral Pulse Wave Analysis Technique to Detect Aortic Valve State in Continuous-Flow LVADs1

We present a quasi-real-time coherent sampling approach that combines the high-bandwidth and high-fidelity signal acquisition of equivalent-time optical sampling with real-time digital signal processing and equalization algorithms. The quasi-real-time concept enables feasibility studies of optical communication at symbol rates beyond the bandwidth of conventional digitizer approaches. Here we demonstrate the technique using a 107-GBd polarization-division-multiplexed quadrature phase shift keyed signal.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

This paper considers an implementation of a real-time signal processor for high resolution SAR (synthetic aperture radar) imaging. In many tasks, we need the SAR imaging take in time, so the real-time processor becomes more and more important. On the basic SAR imaging principle, it is well known that the high range resolution depends on the transmitted signal bandwidth, while high azimuth resolution results from the space Doppler frequency bandwidth. With the increase of frequency bandwidth, the rate of sampling increases, so a fast processor is required in high resolution real-time SAR imaging. To address this need, we discuss the way in which the high speed general DSP and special DSP are applied for high resolution real-time imaging, and good performance is obtained.

In this paper we investigate the efficacy of applying the coupled field back-propagation algorithm as a post-compensation method for nonlinearity mitigation in a coherently detected fibre optic long-haul system using multi-band orthogonal frequency division multiplexed signals. Specifically, we analyze the impact of varying the band-spacing and the number of bands. We find that its efficacy is higher for largely spaced bands and a small number of bands. Additionally, we propose a method to include the Four Wave Mixing compensating term within the coupled field method to provide simplified means of multichannel compensation. We conclude that this method is more efficient in improving the performance especially for small band spacings. The coupled field method proves to be an interesting choice for the implementation of receiver-based real-time digital signal processing.

We introduce and describe the initial evaluation of a new low-cost augmented violin prototype, with research focused on the user experience when playing such hybrid physical-digital instruments, and the exploration of novel interactive performance techniques. Another goal of this work is wider platform accessibility for players, via a simple `do-it-yourself' approach described by the design herein. While the hardware and software elements are open source, the build process can nonetheless require non-insignificant investments of time and money, as well as basic electronics construction skills. These have been kept to a minimum wherever possible. Our initial prototype is based upon an inexpensive electric violin that is widely available online for approximately $200 USD. This serves as the starting point for construction, to which the design adds local Digital Signal Processing (DSP), gestural sensing, and sound output. Real-time DSP algorithms are running on a mobile device, which also incorporates orientation/gesture sensors for parameter mapping, with the resulting sound amplified and rendered via small loudspeakers mounted on the instrument. The platform combines all necessary elements for digitally-mediated interactive performance; the need for a traditional computer only arises when developing new DSP algorithms for the platform. An initial exploratory evaluation with users is presented, in which performers explore different possibilities with the proposed platform (various DSP implementations, mapping schemes, physical setups, etc.) in order to better establish the needs of the performing artist. Based on these results, future work is outlined leading towards the development of a complete quartet of instruments.

Field programmable gate arrays (FPGAs) are attractive for a digital spectrometer due to its advantages of digital signal processing. However, how to improve the versatility of the spectrometer and increase the operating frequency of the digital shaper has gradually become a limitation that needs to be resolved in the FPGA-based spectrometer. A solution to improve the universality of the FPGA-based digital spectroscopy system is presented in this work, and the implementation of the real-time digital signal processing unit is improved to obtain a higher operating frequency, and then the optimal parameters of the digital trapezoidal shaper and the processing unit are also discussed through a series of experiments; finally, a FPGA-based digital spectrometer is developed. With the HPGe detector, the spectrometer achieves excellent energy resolution performance of 0.35% at 662 keV, 0.25% at 1173.2 keV, and 0.23% at 1332.5 keV.

The role of software is becoming increasingly important in the implementation of digital signal processing (DSP) applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state of the art in programming language and compiler technology for DSP software implementation. In particular, we review techniques for high-level block-diagram-based modeling of DSP applications; the translation of block-diagram specifications into efficient C programs using global target-independent optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors using architecture-specific and retargetable back-end optimizations. We also point out important directions for further investigation.