Real-time signal processing in field programmable gate array based digital gamma-ray spectrometer.

Field Programmable Gate Arrays (FPGAs) provide flexible computational architectures that are ideal for digital signal processing (DSP). With support of a NIH/NIDCD SBIR grant, we are developing an open FPGA platform for the speech, hearing, and acoustics research communities. The advantage of using FPGAs in a computational platform over conventional CPU approaches is the ability to implement low-latency high-performance signal processing with deterministic latencies. The hardware portion of the platform includes an audio codec and an Intel System-on-Chip (SoC) FPGA that contains ARM CPUs alongside the computational fabric that allows custom data plane designs. Development uses Mathwork’s Simulink that allows exploration and simulation of signal processing algorithms. Once a Simulink model has been developed to implement audio processing in either the time domain or frequency domain, VHDL code can be generated that implements the desired signal processing. The VHDL code is then implemented in the FPGA computational fabric where the FPGA functions as a real-time signal processor. We are currently soliciting ideas/feedback from the speech, hearing, and acoustic communities as to what features they would like to see in the next iteration of the open FPGA-based computational platform. [NIH/NIDCD R44DC015443: www.openspeechtools.com]

Ultrasonic nondestructive evaluation (NDE) has been widely used in quality assessment and failure analysis for critical structures. The NDE system is commonly designed on microcontrollers and digital signal processors, which fall short of meeting the demands of high speed and requirements of adaptability. This requires reconfigurable computing devices to implement the system. This study aims to build a prototype real-time ultrasonic signal processing platform using Field Programmable Gate Array (FPGA). The platform acquires ultrasound data at the speed of 100 MSPS. The embedded system running on an FPGA is reprogrammable to evaluate signal processing algorithms and NDE methods. To demonstrate the system, a split spectrum processing algorithm is implemented and the result is displayed on a touch screen LCD. Thanks to the flexibility of FPGA, the platform is not limited to ultrasound NDE application. It may have a broader impact on future project development for signal processing research and education.

A multifunction, single platform RF sensor capable of performing target acquisition and tracking, combat identification, high data rate communications, and active protection is of interest to the USA army. The sensor ultimately must tie affordable and the size minimized to meet the demands of a rapidly deployable force. To address these needs, the Army Research Laboratory has built and tested a multifunction radar test bed capable of performing multiple tasks simultaneously at K/sub a/-band. The system has integrated high-end RF components together with commercial-off-the-shelf (COTS) signal processing technology. Key elements of the test bed are a commercial direct digital synthesizer (DDS) for adaptable waveform generation, multiple COTS field programmable gate array (FPGA) processors for real-time data acquisition and signal processing, a COTS FPGA based multi-port input/output (I/O) board programmed for radar timing and control, and an electronically scanned antenna (ESA) based upon a Rotman lens beam-former with active elements for multi-beam generation. The radar is capable of transmitting and receiving two simultaneous and independent beams in azimuth with up to 3 GHz of bandwidth and up to 8 watts of average power. The current configuration uses one beam for a radar target acquisition function and the other for a high data rate communication channel. The emphasis of this paper is on the radar's waveform generation and signal processing capability.

System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for real-time signal processing due to their low, deterministic latency and high performance. To showcase the utility of our open FPGA computational platform for real-time audio signal processing and computational modeling, several applications have been implemented. We have ported the openMHA hearing aid software [1] to our platform to show that pre-existing audio processing software can be implemented in SoC FPGAs by making external audio interfaces show up as a sound card. To highlight the ability to perform real-time computational modeling on our performance platform, we are implementing a real-time version of Laurel Carney’s auditory-nerve model [2] running in its own custom accelerator in the FPGA fabric. To illustrate the ability to develop DSP algorithms in MathWork’s Simulink and then implement them in the FPGA fabric we have taken several algorithms from Issa Panahi’s group [3] to show both frame-based processing (noise reduction) and sample-based processing (dynamic range compression). Finally, we show that the platform can be used to visualize audio signals using a real-time spectrogram where FFTs are computed in the FPGA fabric. [1] www.openmha.org. [2] JASA 126, 2390–2412. [3] www.utdallas.edu/ssprl/hearing-aid-project/.

The burgeoning interest within the space community in digital beamforming is largely attributable to the superior flexibility that satellites with active antenna systems offer for a wide range of applications, notably in communication services. This paper delves into the analysis and practical implementation of a Digital Beamforming and Digital Down Conversion (DDC) chain, leveraging a high-speed Analog-to-Digital Converter (ADC) certified for space applications alongside a high-performance Field-Programmable Gate Array (FPGA). The proposed design strategy focuses on optimizing resource efficiency and minimizing power consumption by strategically sequencing the beamformer processor ahead of the complex down-conversion operation. This innovative approach entails the application of demodulation and low-pass filtering exclusively to the aggregated beam channel, culminating in a marked reduction in the requisite digital signal processing resources relative to traditional, more resource-intensive digital beamforming and DDC architectures. In the experimental validation, an evaluation board integrating a high-speed ADC and a FPGA was utilized. This setup facilitated the empirical validation of the design’s efficacy by applying various RF input signals to the digital beamforming receiver system. The ADC employed is capable of high-resolution signal processing, while the FPGA provides the necessary computational flexibility and speed for real-time digital signal processing tasks. The findings underscore the potential of this design to significantly enhance the efficiency and performance of digital beamforming systems in space applications.

Realising radar high-speed real-time signal processing under the space-borne environment is a worldwide research difficult point. Commercial Quartus devices required for high-speed processing are hardened and consolidated in high radiation environments. This study realises high-speed real-time radar signal processing in space-borne environment for doing the reinforced design of commercial Quartus chip for pulse compression algorithm. The article first analysed the failure modes of high-performance FPGAs in a space-borne environment in China: a highly efficient parallel pipeline architecture with 8-8 K points is designed; control registers, state machine registers, on-chip RAM, and other easy-to-flip positions have been fully reinforced for the pulse compression algorithm. The system realises 200 M real-time processing capability after integration. Single-event fault injection tests were performed on key signals such as system control, and the test results verified the effectiveness of the reinforcement. The fault tolerance of the system has been significantly improved to ensure the normal operation of the FPGA.

1-Gb/s multimedia service upstream transmission in real-time digital signal processing (DSP)-based orthogonal frequency division multiplexing-passive optical network (OFDM-PON) is experimentally demonstrated with centralized light source (CLS) configuration in this paper. After transmitted over 25km standard single mode fiber (SSMF) with-16.5dBm optical power at receiver, the bit error rate (BER) is 9.5×10-11. The implementations of digital domain up-conversion and down-conversion based on field programmable gate array (FPGA) are introduced, which can reduce the cost of in-phase and quadrature (IQ) radio frequency mixers utilized at transmitter and receiver. A new structure of frequency synchronization unit (FSU) designed in FPGA is also proposed to cope with the frequency shifting at receiver.

In this article, we review our recent research progresses on the field programmable gate array (FPGA)-based real-time generation and reception of orthogonal frequency-division multiplexing (OFDM) signals for the short-reach direct-detection system and radio-over-fiber (RoF) system. With the low-complexity real-time digital signal processing (DSP) algorithms, a high-definition video signal with a data rate of 2.97 Gb/s transmission over 20 km single-mode fiber (SMF) without using forward error correction (FEC) technique is experimentally demonstrated in an intensity-modulated direct-detection optical OFDM system in the presence of sampling frequency offset (SFO). In addition, a real-time X-band OFDM-RoF system with heterodyne detection was also realized. With the help of Reed-Solomon coding with a multiplesymbol interleaving/de-interleaving scheme, the 16-ary quadrature amplitude modulation (16-QAM) OFDM-RoF signals over 10-m wireless and 2.26-km SMF-28 link was successfully achieved with a post-FEC bit error rate less than 1×10-9.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

This paper considers an implementation of a real-time signal processor for high resolution SAR (synthetic aperture radar) imaging. In many tasks, we need the SAR imaging take in time, so the real-time processor becomes more and more important. On the basic SAR imaging principle, it is well known that the high range resolution depends on the transmitted signal bandwidth, while high azimuth resolution results from the space Doppler frequency bandwidth. With the increase of frequency bandwidth, the rate of sampling increases, so a fast processor is required in high resolution real-time SAR imaging. To address this need, we discuss the way in which the high speed general DSP and special DSP are applied for high resolution real-time imaging, and good performance is obtained.

Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.

Onboard millimeter-wave radar is one way to improve helicopter flight safety at low altitudes in difficult meteorological conditions. Low-altitude flight is associated with the risk of collision with low-visibility obstacles such as power lines. Since power lines have the property of polarization anisotropy, it is necessary to use radar polarimetry methods to increase the radar visibility of such obstacles for detection. This paper investigates the possibility of identifying low-visibility polarization-anisotropic objects, such as power lines, in polarimetric images obtained by onboard helicopter radars to warn the pilot about the danger of a collision with a low-visibility object. Consequently, the use of a polarimetric radar with a polarization modulation of the emitted signal, the two-channel polarization synchronous reception of reflected signals and Eigenvalue signal processing in real time was proposed, aiming to eliminate the dependence of reflected signals on the spatial orientation of power transmission line wires. Additionally, an optimal algorithm for adaptive polarization selection, obtained by the maximum likelihood method, was proposed to detect such objects against the background of the underlying surface. The effectiveness of the proposed algorithm was tested using computer modeling methods. Moreover, a W-band polarimetric radar system was designed for experimental studies of this concept. The developed radar system provides digital real-time signal processing and the reconstruction of composite polarimetric images. It displays information about the polarization characteristics of the objects in the scanned area and the results of their polarization selection. Therefore, the system informs the pilot about dangerous objects along the helicopter’s route. Radar experimental tests in actual environmental conditions have confirmed the proposed concept’s correctness and the proposed method and algorithm’s effectiveness.

Due to the pandemic, the vast majority of courses taught in the second half of 2020 proceeded online. We discuss the conversion of a Real-time Digital Signal Processing (DSP) course with traditional in-person hands-on labs to a hybrid (in-person and online) setting. This senior-level undergraduate course is built around the development and testing of DSP software. In the online version of the course, students use a small microcontroller kit and a USB oscilloscope, and they work in online teams. We describe the lab projects and we highlight the mechanisms that enable the students to collaborate on labs. We provide early feedback from students from the first offering of the modified course, and conclude with a list of planned improvements.

A real-time digital signal processing (DSP)- enabled digital subcarrier cross-connect (DSXC) with resampling filters for channel frequency translation is demonstrated in this paper. This circuit-based DSXC supports flexible and fine data-rate subcarrier channel granularities, offering a low-latency data plane, transparency to modulation formats, and the capability of compensating for transmission impairments in the digital domain. The presented 8 × 8 DSXC demonstrator makes use of a Virtex-7 field programmable gate array (FPGA) platform, which supports any-to-any switching of eight subcarrier channels with mixed modulation formats and data rates. Digital resampling filters enable frequency translation of subcarrier channels at the cross-connect with much reduced processing requirements for the FPGA resources in comparison to the traditional technique based on in-phase/quadrature mixing and filtering.

Emerging trends in design of real-time digital signal processing systems indicate that in the future, a significant amount of performance improvement can be achieved using dynamically reconfigurable embedded architectures consisting of reconfigurable, general-purpose components. Although embedded real-time systems have long been prevailing in our society, no firm scientific base has been established yet to handle timing requirements in a systematic manner in real-time embedded computing. Because of this lack of the scientific base, many embedded systems have been designed in an ad hoc manner and most of them have been customized to specific applications, showing inflexibility for the other type of applications. This paper proposes a dynamically reconfigurable embedded architecture which bridges the gap between the embedded system and ASICs. This architecture combines a reconfigurable hardware processing unit with a software programmable processor. The main goal is to take advantage of the capabilities of both resources. While the processor takes care of all sequential computations the reconfigurable hardware takes specialized vector operations. With such integrated system architecture, specific properties of applications, such as parallelism, regularity of computation and data granularity can be exploited by creating custom operators, pipelines and interconnection pathways. To handle the conflicting requirements of being a flexible architecture and implement some application-specific algorithms, a dynamically reconfigurable embedded architecture is proposed. The proposed architecture consists of arithmetic operation-level configurable modules interconnected through multiple data buses that can be logically configured to form one or more pipelines before a specific application is initiated and remains unchanged till the completion of the application. This architecture is targeted at high throughput and real time signal processing applications. The idea of dynamic reconfiguration - changing a circuit while it is operating - is exploited. In particular, we illustrate how dynamic reconfiguration can achieve significant performance improvement.