A multirate double-sampling sigma delta modulator for multi-standard wireless radio receivers

This paper reports a fourth-order continuous-time (CT) delta-sigma modulator (DSM) that features a single biquad integrator, a passive integrator and an active integrator. A benefit is the low power consumption using only two opamps in comparison to 4 power-hungry opamps in the conventional fourth-order DSM. The proposed CT-DSM employs two Miller compensation opamps to satisfy the gain bandwidth (GBW) requirement and the loop gain requirement. In this design, the GBW is only 1.65 times higher than the sampling frequency and the open loop DC gain is much higher than the oversampling rate. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to complete the CT DSM including the feedback paths. The effective number of bits of the proposed CT-DSM is 14 bits with a peak SNR of 90.5 dB. The proposed design has a maximum bandwidth of 2 MHz with a power consumption less than 3 mW. Thus, it achieves an excellent figure of merit around 175 dB compared to existing state-of-the-art.

This paper is devoted to the discussion of a new kind of sigma-delta modulator as signal expression, by which the higher-bit input signal can be represented as a lower-bit digital signal. The quantized noise shaping and noise frequency spectrum are discussed and compared with the conventional sigma-delta modulator. The theoretic analysis shows that the new modulator is stable. A kind of DDC based on this modulator is designed and simulated.

We present a globally stable arbitrary-order single-bit delta-sigma modulator architecture with continuous-time loop filtering. Using Lyapunov arguments and the method of equivalent control, it is shown that stability is guaranteed for any input signal with peak magnitude less than L>0, where -L and +L denote the quantization levels. The design augments the conventional delta-sigma modulator with switching feedback and the use of distinct operating modes; the additional circuitry required for the implementation of these stabilizing measures is nominal. For a given noise transfer function and fixed oversampling ratio, the new architecture achieves the same peak signal-to-noise-plus-distortion ratio as a traditional delta-sigma modulator. The proposed design can also yield near-peak performance for inputs which destabilize the conventional delta-sigma data converter. Simulation results are provided for the proposed modulator and a comparable standard interpolative design.

This article reports a fourth-order continuous-time (CT) delta–sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain–bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.

A 2-bit adaptive sigma delta modulation system that inherently eliminates the idle tones present in conventional and other adaptive sigma delta systems is described. The system incorporates both memory and look-ahead instantaneous step-size estimations and, as shown by computer simulation results apart from eliminating the unwanted idle tones despite dithering, it offers improved SNR performance and extended dynamic range.

Sigma-delta modulation is a common technique used in analog-to-digital conversion. It has been shown that it can be implemented in a field-programmable gate array (FPGA) using minimal external analog components. Zhao et al. demonstrated that energy of scintillation pulses can be computed by adding up all the elements on the output from a conventional 1-bit sigmadelta modulator. However, for parameters selected for a suitable resolution and dynamic range, the system passes through a period of saturation. During saturation, information about the shape of the pulse is lost even though the integrated energy remains preserved. We present the design of a 2-bit version of the sigmadelta modulator that makes use of a nonlinear adaptive digital-to-analog converter (DAC) that keeps the system unsaturated. Each output bit is scaled by one of the four possible values the DAC can take, resulting in a 2-bit modulation. We have demonstrated that the 2-bit modulation retains information about the pulse shape.

As a method for constructing a discrete-time binary control system, we propose a method using a variable-order delta-sigma modulator. By making the order of the modulator variable, the weaknesses of the conventional delta-sigma modulator approach can be overcome, but the dynamic switching of the order causes the modulator to become unstable. Therefore, we specified the cause of instability and showed how to overcome it. The method was applied to temperature control by zero cross-switching of AC voltage in an electric furnace with a resistant heater, and the effectiveness of the proposed method was shown.

Conventional sigma delta A/D convertor was composed of sigma delta modulator and digital decimation filter. By anti-aliasing filter and sampling-holder circuit, the AC analog signal functioned as DC signal to guarantee the steady conversion precision. Based on the characters of sigma delta modulator, A/D conversion can be finished by only sigma delta modulator without any other accessory circuit. Considering the calculating data is a limit long in a practical application, the analog signal were obtained by calculating the output data stream of sigma delta modulator. Furthermore, the processing will be simpler to approximate the difference every two adjacent sampling point as same. The calculating approach decreased the error which brought by the anti-aliasing filter, sampling-holder and digital decimation filter. By omitting these accessories, the circuit is simply and easy be used in a practical application. A good result was given by data analysis for the processing method

The high-frequency performance of switched-capacitor filters is bounded mainly by the finite gain bandwidth product of operational amplifiers. In this paper, the effects of finite gain bandwidth product of operational amplifiers on the performance of FIR (transversal) filters using such amplifiers as delay elements (canonical circuit) is analyzed. Next, a new low-power consumption FIR switched-capacitor circuit for high frequencies, which we call a parallel cyclic-type circuit (PCTC), is proposed. The proposed circuit does not use operational amplifiers as delay elements. Instead, switches and capacitors are used for both the delaying and the weighting operations. We present a basic circuit using subblocks, a circuit with reduced number of capacitors, and a modified circuit having plural operational amplifiers for higher-frequency use. We then show the design of a fourthorder FIR filter employing PCTC. Under the condition that sampling frequency is one-half of unity gain frequency of operational amplifier, computer simulations of fourth-order transversal switched-capacitor filters with canonical circuit and that with parallel cyclic-type circuit are performed and the experimental results of these circuits using discrete components are also given. Both demonstrate that the parallel cyclic-type circuit has significantly better performance than the canonical circuit.

This paper proposes a novel low-power operational amplifier (OPAMP) using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs). By introducing dynamic operation, power consumption of the proposed OPAMP has been significantly reduced without compromising with other design parameters like gain, slew rate etc. In addition, common mode feedback (CMFB) and internal frequency compensation have been used to ensure good common mode rejection ratio (CMRR) and stability of the OPAMP, respectively. In order to demonstrate the proposed idea, low power OPAMP is designed and simulated using in-house a-IGZO TFT model in Cadence Virtuoso. Circuit simulations have been carried out at a supply voltage and device channel length of 10 V and 20 \(\upmu \)m, respectively. From simulations, a gain of 30 dB and unity gain bandwidth of 106.8 kHz with a phase margin of 63\(^{\circ }\) were noticed. The power consumed by the proposed OPAMP is 146.8 \(\upmu \)W, which is significantly lower compared to the OPAMPs implemented with various TFT technologies. The proposed OPAMP circuit would find potential applications in various real-world large area applications that need flexible electronics with low-power consumption like bio-medical and wearable devices.

This article presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes’ information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving paths, thus reducing analog hardware overheads. Meanwhile, we linearize the digital feed-forward paths through injected dithering. We present the derivation of extrapolating TI DSM starting from a single-channel DSM, while we also list and compare several conventional TI approaches. Implemented in 28-nm CMOS, this modulator achieves an equivalent output-sampling rate of 2.08 GS/s, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$208\times $ </tex-math></inline-formula> oversampling ratio (OSR), and a signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 86.1 dB/98 dB with 5-MHz bandwidth (BW). The power consumption is 23.1 mW, which results in a Schreier Figure of Merit (FoM) of 169.5 dB.

A delta-sigma-modulated intermediate-frequency-over-fiber (IFoF) transmission system assisted by a correlative-level coding technique is proposed and experimentally demonstrated. Unlike conventional delta-sigma IFoF systems with multiple output levels to achieve higher signal quality or larger capacity, a correlative-level encoder is exploited as a second modulator preceded by the delta-sigma modulator. The encoder compresses the bandwidth of the delta-sigma modulated signal by creating a correlation between adjacent signal symbols. As a result, the sampling frequency of the delta-sigma modulator in the proposed system can be increased beyond the transmission bandwidth of the IFoF system, considerably improving the in-band signal quality and the transmission capacity over the conventional multi-level approach. This is because the quantization noise from the delta-sigma modulation in the proposed scheme is more aggressively pushed away from the signal bandwidth with the high sampling frequency. According to experimental results, the proposed link provides at least a 40% larger transmission capacity for similar in-band signal quality or 2.1% better average EVM performance for the same capacity than the conventional four-level pulse-amplitude-modulation delta-sigma IFoF systems.

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

In multistandard radio receivers, the hardware should be configurable or programmable for the reception of different types of signals having different symbol rates. The decimation by a non-integer factor becomes a critical functionality of the multistandard radio. The Cascaded Integrator-Comb (CIC) filters are commonly used for decimation by an integer. By using polynomial interpolation filter between integrator and comb stages of CIC, and non-integer delay in the feed-forward branch of the comb stage, we achieve improved attenuation for the aliasing frequency components, and we make possible to use this type of structure for decimation by a non-integer factor. We name this structure as a programmable fractional CIC filter structure. This paper presents an efficient fractional structure for flexible decimation in the multistandard radio receivers. This structure is based on the so-called modified comb filter using the programmable fractional CIC principle. The main advantages of the proposed structure are flexibility and programmability with increased attenuation for aliasing frequency components.

The piezoelectric actuators have high resolution, wide operating frequency and low power consumption, but they suffer hysteresis which affects their linearity. In this paper are presented comparatively the analog and digital techniques for improvement (reducing) of nonlinear behavior of this type of actuators using charge amplifiers. First an analog charge amplifier and its performance analysis are presented. Then a model of digital charge amplifier with linearity performance considerably improved (91% reduced), but which shows a pronounced drift is presented. In the last section several methods for drift reducing are presented and analyzed, one of them having a reduction with 87%. A number of functional diagrams and response graphs for the developed techniques and methods are presented. Introduction The application area of the piezoelectric actuators has been spectacular developed, especially due to their remarkable qualities. Compared to other nano-positioning actuators, these have high resolution, high force, wide operating frequency and low power consumption. It is enough to mention some of their applications [1, 2, 3]: in micro and nano-devices for mechanical positioning with below micrometrics accuracy (optical and electronics microscopy, high precision cutting devices (error correction), robotics and positioning of magnetic heads and optical recordingplayback); in deformable mirrors (adaptive optics systems); in ultrasonic motors; in the impact controlled on/off devices; in fuel injectors of diesel engines etc. But, the piezoelectric materials have important non-linear characteristics determi-ned by the existence of hysteresis and creep, which can reduce the positioning accuracy of a piezoelectric actuator. When it is applied to a piezoelectric actuator a sudden voltage, the length will quickly respond then it will change slowly due to the creep effect. Creep is the polarization result of the piezoelectric actuator which continues to change after the applied voltage reaches its final value. Commonly, this effect is an issue at low frequencies and it is not important for higher frequencies [4]. Hysteresis is another undesired effect: when the input voltage is gradually increased, the actuator displacement is different from when the voltage is decreased for the same voltage value applied. For hysteresis reducing, many techniques have been implemented: the model-based control [5]; the displacement feedback control [6]; the charge control [7]. Without going into details, it is worth mentioning that, none of these techniques do not provide an acceptably hysteresis dimi-nution to allow the piezoelectric actuators to do the very high precisions displacement. In this paper, a model of digital charge amplifier is presented. By this model, a significant reduction of the piezoelectric actuators nonlinear behaviour is obtained. 94 | T h e 3 9 t h A R A P r o c e e d i n g s In the following sections we present this digital model. The analog charge amplifier To make the transition to digital charge amplifier, we present a simple analog charge amplifier in this section. In Figure 1(a) the circuit diagram of this analog charge amplifier is shown. It contains a comparator (Ʃ) and amplifier (K), a stack piezoelectric (SP) with capacity, Cpa, a sensing capacitor with capacitance, CS. R1 is used to model the operational amplifier (OA) input terminal leakage, and R2 is due to the leakage of the sensing capacitor. The circuit feedback loop is used to equalize the reference voltage, Vr, with the actual voltage across the sensing capacitor. If the OA, SP and sensing capacitor would be ideal, R1 and R2 can be removed and ideal Laplace transfer function would be: