Stable one-bit delta-sigma modulators based on switching control

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

Sigma-Delta modulators (SDMs) are capable of shaping the quantization noise out of a specific frequency band defined by their noise transfer function (NTF). A single-bit output SDM pose further advantages in applications that would typically require a multi-bit DAC, since then only a single-bit DAC is required, which is much easier to design and is inherently linear in comparison to a multi-bit one. Look-ahead SDMs have been proposed to enhance the signal-to-noise-and-distortion-ratio (SNDR) and the output bandwidth of conventional single-bit SDMs. Multi-Step Look-Ahead sigma-delta modulators (MSLA SDMs) further reduce the hardware complexity required for the implementation of typical look-ahead SDMs while maintaining their performance advantages. In this work the architecture and the benefits of the MSLA SDMs are showcased. Finally the advantages of the MSLA SDMs over single-bit conventional ones are demonstrated and several hardware implementation choices for design optimization are discussed.

A novel multirate double-sampling sigma delta modulator is proposed for the low power A/D converter for multi-standard wireless applications. A cascade 2-2 structure is designed for the modulator. The multirate technique reduces the sampling rate of the 1st stage integrator to relax the performance requirements of the operational amplifiers(OPAMP), which in turn results in low power consumption. The double-sampling technique is adopted to update the integrator output of the switched capacitor circuit during the both clock phases of the master clock. The sampling frequency is twice of the master clock frequency. The clock frequency can be halved to relax the settling time of the OPAMPs to achieve the similar performance concerning the signal to noise ratio with the conventional sigma delta modulator, which decreases the power dissipation. In comparison with the conventional double-sampling sigma delta modulator topology, the proposed modulator architecture obtains the similar performance with a low slewrate requirement of the 1st stage integrator. The power dissipation is effectively decreased.

A low power second order hybrid loopfilter Sigma-Delta modulator with high resolution is presented. The structure is composed by a first active integrator followed by a switched-capacitor (SC) integrator. This modulator architecture exploits the coefficient scaling property of the active integrator, while the SC integrator is modified to shift its pole from inside the unit circle to z=1 at DC in the z-domain. Poles of the loopfilter are zeroes of the noise transfer function (NTF). As a result the NTF zero is also shifted to z=1. This NTF zero compensation for the SC integrator will result in better in-band noise suppression & improved noise shaping. The second order hybrid sigma-delta modulator with a 4-bit quantizer and an oversampling ratio (OSR) of 32 is simulated in simulink. The modulator can achieve 89dB SNDR with a dynamic range of 91dB.

Sigma delta modulation is a popular technique for high-resolution analog-to-digital conversion and digital-to-analog conversion. We investigate chaotic phenomena in multibit first-order sigma-delta modulators. Particular attention is placed on the occurrence of periodic orbits or limit cycles. These may result in idle tones audible to the listener when sigma-delta modulation is used for audio signal processing. One suggested method of eliminating idle tones is the operation of a sigma delta modulator in the chaotic regime. Unfortunately, chaotic modulation of a first order sigma delta modulator is a poor system for signal processing. We show that minor variations on a traditional first order sigma-delta modulator, together with a multibit implementation, may be used to produce an effective, stable chaotic modulator that accurately encodes the input and helps remove the presence of idle tones. (c) 2001 American Institute of Physics.

This brief presents a power reduction technique for continuous time sigma–delta modulators (CTSDMs). The approach consists of two elements. First, a passive low-pass filter is added in front of the modulator’s loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low-pass filter also changes the modulator’s loop gain, and hence affects the noise transfer functions (NTFs) and signal transfer functions (STFs), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs, where the amount of high-frequency components in the loop is excessive. To showcase the technique, a self-oscillating sigma–delta modulator (which is a dedicated type of one-bit CTSDM) was implemented in a 65-nm CMOS process. It achieves a peak signal to noise and distortion ratio of 63 dB over a 20-MHz bandwidth at a power consumption of 1.7 mW while occupying a very small chip area of only 0.009 mm2.

Sigma-delta modulation is a common technique used in analog-to-digital conversion. It has been shown that it can be implemented in a field-programmable gate array (FPGA) using minimal external analog components. Zhao et al. demonstrated that energy of scintillation pulses can be computed by adding up all the elements on the output from a conventional 1-bit sigmadelta modulator. However, for parameters selected for a suitable resolution and dynamic range, the system passes through a period of saturation. During saturation, information about the shape of the pulse is lost even though the integrated energy remains preserved. We present the design of a 2-bit version of the sigmadelta modulator that makes use of a nonlinear adaptive digital-to-analog converter (DAC) that keeps the system unsaturated. Each output bit is scaled by one of the four possible values the DAC can take, resulting in a 2-bit modulation. We have demonstrated that the 2-bit modulation retains information about the pulse shape.

A self-adaptive Sigma-Delta modulator, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance, is presented in this paper. Traditional Sigma-Delta modulator mainly focused on using a 2nd order sensing element to improve the SNR, whereas this paper presents a 5th order Sigma-Delta modulator to obtain higher SNR. Specifically, an additional 3rd order digital loop integrator is inserted between the AFE and the quantizer, which increases overall loop order to produce much higher SNR for Sigma-Delta modulator and the parameters of the 3rd order digital loop integrator are optimized by swarm intelligent algorithm. Simulation results with respect to the proposed 5th order Sigma-Delta modulator, SNR >122 dB and the noise floor under -170dB are obtained in frequency range of [5-150Hz]. In further simulation, the robustness of the proposed 5th order Sigma-Delta modulator is analyzed.

The stability of a single-quantizer Sigma Delta modulator in terms of its noise transfer function is studied. It is shown that stability is conditional upon the input signal, and an explicit formula for the set of all inputs which result in stable behavior is given. In addition, the authors compare the set of modulators stable with zero input to the sets given by several existing rules of thumb and find that these criteria are neither necessary, nor in some cases sufficient, to ensure stability.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multi-carrier systems such as Orthogonal Frequency Division Multiplexing (OFDM) require linear amplification and have low power efficiency because of high peak-to-average power ratio (PAPR). In an Envelope Pulse-Width Modulation (EPWM) transmitter, the envelope component of a linear modulation wave is converted to a PWM signal by a delta-sigma (Delta-Sigma) modulator while the phase component modulates the carrier signal. The distortion-free amplitude multiplexing of the PWM and PM signals enables the power amplifier to achieve maximum power efficiency. In this paper, EPWM transmitter characteristics such as noise power spectral density and SNR will be analyzed. The application of the EPWM transmitter to OFDM signals will also be explored. From the simulation results, the Delta-Sigma modulator with an oversampling ratio of 32 provides sufficient in-band SNR and adjacent channel power ratio required for the IEEE 802.11a OFDM system.

A characterization method for verifying stability and measuring the performance quality of arbitrary noise transfer functions for the delta-sigma modulator is presented. The method consists of first obtaining the maximum stable input range sweep in the pass-band. The variance estimate can then be used to make a sharper upper limit for maximum allowed input range. This can then be used to measure the global SNR performance in the pass-band. The proposed method enables us to make a comprehensive comparison between arbitrary noise transfer function designs and it can also be used to automate the design of noise transfer functions

This paper presents a fourth-order tunable continuous time (CT) bandpass (BP) sigma-delta modulator with fractional delays (fSigmaDelta) fabricated in 0.5 mum/f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> = 47 GHz SiGe technology. The modulator is a fully differential g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C based circuit powered from from a 3.3 V supply and occupies 2.3 mm times 2.3 mm. At sampling rates from f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> = 600 MHz to f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> = 1.2 GHz and a single-tone input signal, within a bandwidth of BW = 20 kHz, the modulator demonstrates maximal SNR = 50 dB and maximal dynamic range DR = 47 dB. The center frequency notch of the noise transfer function (NTF) is tunable from 185 MHz to 289 MHz, while the resonator itself can achieve 60 MHz to 295 MHz. This prototype design experimentally confirms validity of the suggested analytical models and design methodology.

This paper presents the system-level design and behavioural implementation of a second-order continuous-time (CT)sigma-delta modulator for high-resolution, low-frequency sensing applications. The modulator architecture is synthesized using the MATLAB Delta-Sigma Toolbox and implemented behaviorally in Cadence Virtuoso using Verilog-A models. A cascade of integrators feed-forward (CIFF) architecture with a 1-bit quantizer and an oversampling ratio (OSR) of 12 is employed to achieve high resolution while maintaining stability. The discrete-time noise transfer function (NTF) is transformed to its continuous-time equivalent using the impulseinvariant transformation with an NRZ feedback DAC pulse. Simulation results demonstrate practical second-order noise shaping. For a 900 mV, 1 Hz sinusoidal input, the modulator achieves an SNR of 86dB, corresponding to an effective number of bits (ENOB) of 14 bits. The influence of the integrator's finite DC gain and limited gainbandwidth product (GBW) on performance is also evaluated. The results validate the proposed modulator architecture for precision low-bandwidth sensing front-end applications.

This paper presents an elaborate plan and optimization method for designing and implementing low-order band pass digital sigma-delta modulator with high order output dynamic range (DR). The noise suppression in the pass band region of the modulator and high order output DR would be achieved by designing and optimizing the Noise Transfer Function (NTF) based on over sampling ratio (OSR) and desired modulator operational frequency and designing the Signal Transfer Function (STF) by the mean which the optimum gain in desired frequency would be acquired. Designed and optimized modulator has been implemented completely on digital circuits and it would be shown that the first order designed modulator has the output dynamic range of 90dB which corresponds to 15 bits data conversion. Results from various simulations illustrate both the stability and high performance of the design and flexibility of the overall structure.

This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.