System-Level Design and Behavioural Implementation of a Second–Order CT SigmaDelta Modulator

Multi-bit continuous time Sigma Delta ($\Sigma\Delta$) modulators are the necessary drivers of modern high speed and low power analog to digital conversion technology. The use of multi-bit quantization in a continuous Time $\Sigma\Delta$ modulator has been limited because nonlinearity in the DAC (Digital to Analog Converter) of a sigma delta modulator translates directly into nonlinearity of the entire modulator, producing a distorted output. Nonlinearity in the DAC modulates the quantization noise into the signal band, thus degrading its performance. It is desired to estimate this non-linearity and apply a correction to nullify its effects. In this paper, a non-invasive background calibration technique is presented for the mismatch estimation and correction of static mismatches in the feedback DAC elements of a continuous time sigma delta modulator. The proposed design can fit into an existing modulator deploying a multi-bit D.AC. It is demonstrated by simulations that the proposed design achieves over 100dB THD performance across 40MHz signal bandwidth for an OSR (Over Sampling Ratio) of 30. The architecture works well even for topologies with achieving very high performance.

A new fully passive noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. The additional pole increases the efficiency of noise shaping to further 3 dB. So, the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB) is possible. The architecture was applied to the design of a 9.8-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architecture provides 3.8 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

This paper reports a fourth-order continuous-time (CT) delta-sigma modulator (DSM) that features a single biquad integrator, a passive integrator and an active integrator. A benefit is the low power consumption using only two opamps in comparison to 4 power-hungry opamps in the conventional fourth-order DSM. The proposed CT-DSM employs two Miller compensation opamps to satisfy the gain bandwidth (GBW) requirement and the loop gain requirement. In this design, the GBW is only 1.65 times higher than the sampling frequency and the open loop DC gain is much higher than the oversampling rate. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to complete the CT DSM including the feedback paths. The effective number of bits of the proposed CT-DSM is 14 bits with a peak SNR of 90.5 dB. The proposed design has a maximum bandwidth of 2 MHz with a power consumption less than 3 mW. Thus, it achieves an excellent figure of merit around 175 dB compared to existing state-of-the-art.

This brief presents a power reduction technique for continuous time sigma–delta modulators (CTSDMs). The approach consists of two elements. First, a passive low-pass filter is added in front of the modulator’s loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low-pass filter also changes the modulator’s loop gain, and hence affects the noise transfer functions (NTFs) and signal transfer functions (STFs), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs, where the amount of high-frequency components in the loop is excessive. To showcase the technique, a self-oscillating sigma–delta modulator (which is a dedicated type of one-bit CTSDM) was implemented in a 65-nm CMOS process. It achieves a peak signal to noise and distortion ratio of 63 dB over a 20-MHz bandwidth at a power consumption of 1.7 mW while occupying a very small chip area of only 0.009 mm2.

A 4th-order resistive feed-forward continuous time sigma-delta modulator (CTSDM) for a worldwide analog/digital TV-receiver is presented. The proposed hybrid integrator of the modulator is developed in order to save the summing amplifier and reduce total area. In addition, the modulator incorporates the proposed low power operational amplifiers (op-amp) with active feed-forward compensation to reduce power consumption in the loop filter. The prototype chip is implemented in a 55nm CMOS process which occupies 0.132 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurements show that the proposed modulator achieves 80.2dB dynamic range, 75.1dB SNDR, and an effective number of bits (ENOB) of 12.2 bits over 5 MHz signal bandwidth. The figure of merit (FOM) is 0.28 pJ/conversion at 1.3 V supply.

The effect of certain fundamental nonidealities on the resolution of a continuous-time (CT) delta sigma modulator are examined in this paper. We start by talking about the equivalence between an ideal CT delta sigma modulator and its discrete-time (DT) counterpart, then consider the effect of quantizer/DAC propagation delay, clock jitter, and the recently-identified phenomenon of signal-dependent jitter on the ideal performance.

This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V.

This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM's output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM's quantization noise transfer function; 4) DAC's pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed.

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator and low noise amplifier (LNA) with data-weighted average (DWA) technology. A new image-reject low noise amplifier is designed for ECG communication and bio-signal wireless acquisitions. An inter-stage T-structure filter is used in the low noise amplifier design to provide 35-dB image rejection. The DWA technique is used for reducing DAC noise due to component mismatches. Experimental results show the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply, which can be used for electroencephalogram (EEG) or electrocardiogram (ECG) signal acquisition systems by wireless sensor and communication. This provided sensor setup CO2 concentration detecting instruments on chip. Oxygen generator will real time to support when sensor monitor and wireless send bio-signal to doctor or health cloud.

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

A low power second order hybrid loopfilter Sigma-Delta modulator with high resolution is presented. The structure is composed by a first active integrator followed by a switched-capacitor (SC) integrator. This modulator architecture exploits the coefficient scaling property of the active integrator, while the SC integrator is modified to shift its pole from inside the unit circle to z=1 at DC in the z-domain. Poles of the loopfilter are zeroes of the noise transfer function (NTF). As a result the NTF zero is also shifted to z=1. This NTF zero compensation for the SC integrator will result in better in-band noise suppression & improved noise shaping. The second order hybrid sigma-delta modulator with a 4-bit quantizer and an oversampling ratio (OSR) of 32 is simulated in simulink. The modulator can achieve 89dB SNDR with a dynamic range of 91dB.

Photonic digital-to-analog converters (PDACs) have a broad application prospect due to the ability to overcome the non-idealities in electronic circuits. PDACs are usually implemented by quantizing and summing the optical intensities of multiple lasers. The relative intensity noise of laser sources plays a critical role in determining the signal-to-noise ratio (SNR) and effective number of bits (ENOB). We present a detailed noise analysis for PDACs. Both the traditional binary-weighted structure and the recently proposed segmented-weighted structure are investigated. The results show that laser noise imposes a fundamental limit to the maximum SNR and ENOB that can be achieved in binary-weighted PDACs, while segmented PDACs can break this limitation and have a continuously increasing SNR with the quantization bit number (QBN). A novel configuration based on laser multiplexing and balanced detection, to the best of our knowledge, is also proposed and analyzed to increase the number of bits when the number of lasers is limited. Numerical simulations are performed to evaluate the SNR evolution with the QBN in different types of PDACs. The results are in good agreement with the theoretical analysis. Our analysis provides useful insights and can be important guidance for implementing high-performance PDACs.

To meet the demand for high-precision biological signal detection in wearable biomedical devices, this paper proposes the design of a fourth-order discrete-time sigma–delta analog-to-digital converter (ADC) employing a multi-stage noise shaping (MASH) 2-2 architecture. In the first-stage sub-modulator, the first integrator adopts a double-sampling structure, which improves noise shaping performance markedly. A novel common-mode feedback (CMFB) circuit has also been designed, which addresses the phase-dependent loading issue in traditional switched-capacitor networks. Notably, a dynamically activated nonuniform quantization mode is innovatively proposed in the second stage. It integrates 2.5-bit coarse quantization with 2-bit fine quantization in specific intervals, enabling high-precision detection of the small-amplitude quantization errors from the first-stage sub-modulator. In addition, the comparator in this stage integrates feed-forward summation capability and retains input offset voltage storage (IOS) technology to reduce the offset voltage. Meanwhile, the designs of dynamically activated nonuniform quantizer and comparator with integrated summation function have reduced the power consumption of the modulator by 19%. In a 180-nm CMOS process, the modulator occupies a layout area of 0.57[Formula: see text]mm 2 and simulation results indicate a peak signal-to-noise-and-distortion ratio (SNDR) of 113.2[Formula: see text]dB. After processing by the cascaded integrator comb (CIC) decimation filter, the ADC achieves a peak SNDR of 115.6[Formula: see text]dB, an effective number of bits (ENOB) of 18.91 bits and a power consumption of 4.36[Formula: see text]mW under a 1.8[Formula: see text]V supply. These performance metrics correspond to a state-of-the-art figure-of-merit (FoM) of 175.1[Formula: see text]dB.

This article reports a fourth-order continuous-time (CT) delta–sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain–bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.