General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators

Multi-bit continuous time Sigma Delta ($\Sigma\Delta$) modulators are the necessary drivers of modern high speed and low power analog to digital conversion technology. The use of multi-bit quantization in a continuous Time $\Sigma\Delta$ modulator has been limited because nonlinearity in the DAC (Digital to Analog Converter) of a sigma delta modulator translates directly into nonlinearity of the entire modulator, producing a distorted output. Nonlinearity in the DAC modulates the quantization noise into the signal band, thus degrading its performance. It is desired to estimate this non-linearity and apply a correction to nullify its effects. In this paper, a non-invasive background calibration technique is presented for the mismatch estimation and correction of static mismatches in the feedback DAC elements of a continuous time sigma delta modulator. The proposed design can fit into an existing modulator deploying a multi-bit D.AC. It is demonstrated by simulations that the proposed design achieves over 100dB THD performance across 40MHz signal bandwidth for an OSR (Over Sampling Ratio) of 30. The architecture works well even for topologies with achieving very high performance.

The effect of certain fundamental nonidealities on the resolution of a continuous-time (CT) delta sigma modulator are examined in this paper. We start by talking about the equivalence between an ideal CT delta sigma modulator and its discrete-time (DT) counterpart, then consider the effect of quantizer/DAC propagation delay, clock jitter, and the recently-identified phenomenon of signal-dependent jitter on the ideal performance.

This paper presents a 3rd-order continuous time sigma-delta (ΣΔ) modulator (CTSDM) using several low power techniques. A compact architecture of 3rd-order CTSDM is proposed to reduce power dissipation on system level. The loop-filter which is the key block of this CTSDM architecture consists of feedforward p'ath, feedforward amplifier, single-opamp resonator and passive adder. A finite gain bandwidth (GBW) compensation method is used to improve the performance. This modulator is designed with TSMC 65nm CMOS process and archives 80dB SNR in 20MHz signal bandwidth while the FOM is 35fJ/conv.

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

Jitter is the limiting effect for high speed analog-to digital converters with high resolution and wide digitization bandwidth, which are required in receivers in order to support high data rates. The rapid development of digital wireless system has led to a need of high resolution and high speed analog to digital converter. The proper selection of data converters, both analog to digital converters and digital to analog converters (DACs) is one of the most challenging steps in designing software radio. The performance of a data converter is dependent upon the accuracy and stability of the clock supplied to the circuits. When data converter employ a high sampling rate, clocking issues become magnified and significant distortion can be result. This paper describes the effect of aperture jitter on the performance of sigma delta ADC and present analytical evaluation of the performance and mean error power spectrum due to aperture jitter application has favored the use of oversampling delta sigma ADC (analog-to-digital converters) due to their better speed-accuracy tradeoff. Delta-sigma modulator is one of the key building blocks, which can be implemented using DT (discrete-time) and CT (continuous-time) techniques. Compared to their DT counterparts, CT delta-sigma modulators have recently attracted more and more attentions due to their advantages in terms of high speed, low power, low noise and intrinsic anti-aliasing capability. In this paper, we concentrate on the discrete implementation. Section 2 presents an aperture jitter effect in SDM in terms of SNR. In the last few years different authors derived formulas to quantify the SNR limiting effect of jitter in ADCs. While Walden used a worst case approach, Kobayashi presented an exact formula which allows calculating the SNR in the presence of an aperture jitter.

This paper reports a fourth-order continuous-time (CT) delta-sigma modulator (DSM) that features a single biquad integrator, a passive integrator and an active integrator. A benefit is the low power consumption using only two opamps in comparison to 4 power-hungry opamps in the conventional fourth-order DSM. The proposed CT-DSM employs two Miller compensation opamps to satisfy the gain bandwidth (GBW) requirement and the loop gain requirement. In this design, the GBW is only 1.65 times higher than the sampling frequency and the open loop DC gain is much higher than the oversampling rate. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to complete the CT DSM including the feedback paths. The effective number of bits of the proposed CT-DSM is 14 bits with a peak SNR of 90.5 dB. The proposed design has a maximum bandwidth of 2 MHz with a power consumption less than 3 mW. Thus, it achieves an excellent figure of merit around 175 dB compared to existing state-of-the-art.

The parallelism between a first-order sigma-delta modulator and a VCO-based ADC allows to calculate the DFT of the sigma delta sequence using Pulse Frequency Modulation theory. This paper exploits this parallelism to propose a more general model that links continuous time sigma delta modulators of an arbitrary order with Pulse Frequency Modulators. This novel point of view also predicts the spectral contents of a sigma delta encoded sequence beyond the white quantization noise model. The quantization noise can be split in two components, a deterministic one representing the carrier harmonic sidebands of a Pulse Frequency Encoded signal and a noise shaped pseudorandom signal representing the sampling operation. We seize these findings to propose a conjecture on the stability of a sigma delta modulator.

When a continuous time sigma delta modulator (CT ΣΔM) is overloaded, its output signal to quantization noise ratio (SQNR) decreases when the ΣΔM's input power is increased over a certain value. In this paper, the range of quantizer gains that cause a CT ΣΔM to overload is determined, and this range of values is used to determine the maximum input signal power that prevents overload. To validate the predicted maximum input power that prevents overload, 2nd through 5th order CT ΣΔMs are simulated.

The effect of clock jitter on the dynamic range of discrete-time (DT) and continuous-time (CT) sigma-delta modulators is addressed. It is shown that clock jitter in DT modulators mixes with the input signal, while for CT modulators, the jitter mixes with the out-of-band quantization error and elevates the passband noise. The signal-to-noise ratio of CT modulators is shown to be more susceptible to clock jitter than their DT counterparts. Analytical and simulation results are provided.

This brief presents a power reduction technique for continuous time sigma–delta modulators (CTSDMs). The approach consists of two elements. First, a passive low-pass filter is added in front of the modulator’s loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low-pass filter also changes the modulator’s loop gain, and hence affects the noise transfer functions (NTFs) and signal transfer functions (STFs), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs, where the amount of high-frequency components in the loop is excessive. To showcase the technique, a self-oscillating sigma–delta modulator (which is a dedicated type of one-bit CTSDM) was implemented in a 65-nm CMOS process. It achieves a peak signal to noise and distortion ratio of 63 dB over a 20-MHz bandwidth at a power consumption of 1.7 mW while occupying a very small chip area of only 0.009 mm2.

In this work, a method for the concurrent estimation of nonidealities in continuous-time sigma-delta modulators is presented. Several nonidealities can degrade the performance of a sigma-delta modulator, even up to instability of the entire circuit. However, if these nonidealities are known, it is possible to correct for most of them - either in the analog or digital domain. In the past, many techniques for corrections of errors in sigma-delta modulators have been presented. Although these works show good results, most are only able to work on a single or few nonidealities simultaneously. In this paper, a feasible approach for estimating several nonidealities in a joint fashion has been applied to estimate some of the most prominent errors in a continuous-time sigma-delta modulator.

This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.

We designed and simulating delta sigma ADC for the ECG signal processing in order to achieve high signal to quantization noise ratio by using over sampling concept and low resolution ADC and DAC. The Proposed work will contain system level modeling, simulation and implementation of blocks used in delta sigma ADC. It is compared with ideal blocks done in simulation. The system level design of third order feedforward (CIFF) structure of continuous time delta sigma modulator is proposed employed in ADC in order to reduce power consumption. The efficiency of the proposed ADC is measured in terms of noise spectrum, maximum stable input amplitude range, simulation performance and accuracy. The targeted signal to noise ratio (SNR) is more than 90 dB with resolution more than 12 bit.

Continuous-time Sigma-Delta (CT-ΔΣ) modulators are oversampling Analog-to-Digital converters that may provide higher sampling rates and lower power consumption than their discrete counterpart. Whereas approximation errors are established for high-order discrete time ΔΣ modulators, theoretical analysis of the error between the filtered output and the input remain scarce. This paper presents a general framework to study this error: under regularity assumptions on the input and the filtering kernel, we prove for a second-order CT-ΔΣ that the error estimate may be in o(1/N)2, where N is the oversampling ratio. The whole theory is validated by numerical experiments.

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator and low noise amplifier (LNA) with data-weighted average (DWA) technology. A new image-reject low noise amplifier is designed for ECG communication and bio-signal wireless acquisitions. An inter-stage T-structure filter is used in the low noise amplifier design to provide 35-dB image rejection. The DWA technique is used for reducing DAC noise due to component mismatches. Experimental results show the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply, which can be used for electroencephalogram (EEG) or electrocardiogram (ECG) signal acquisition systems by wireless sensor and communication. This provided sensor setup CO2 concentration detecting instruments on chip. Oxygen generator will real time to support when sensor monitor and wireless send bio-signal to doctor or health cloud.