Analysis of timing jitter in bandpass sigma-delta modulators

The effect of certain fundamental nonidealities on the resolution of a continuous-time (CT) delta sigma modulator are examined in this paper. We start by talking about the equivalence between an ideal CT delta sigma modulator and its discrete-time (DT) counterpart, then consider the effect of quantizer/DAC propagation delay, clock jitter, and the recently-identified phenomenon of signal-dependent jitter on the ideal performance.

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM's output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM's quantization noise transfer function; 4) DAC's pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed.

Jitter is the limiting effect for high speed analog-to digital converters with high resolution and wide digitization bandwidth, which are required in receivers in order to support high data rates. The rapid development of digital wireless system has led to a need of high resolution and high speed analog to digital converter. The proper selection of data converters, both analog to digital converters and digital to analog converters (DACs) is one of the most challenging steps in designing software radio. The performance of a data converter is dependent upon the accuracy and stability of the clock supplied to the circuits. When data converter employ a high sampling rate, clocking issues become magnified and significant distortion can be result. This paper describes the effect of aperture jitter on the performance of sigma delta ADC and present analytical evaluation of the performance and mean error power spectrum due to aperture jitter application has favored the use of oversampling delta sigma ADC (analog-to-digital converters) due to their better speed-accuracy tradeoff. Delta-sigma modulator is one of the key building blocks, which can be implemented using DT (discrete-time) and CT (continuous-time) techniques. Compared to their DT counterparts, CT delta-sigma modulators have recently attracted more and more attentions due to their advantages in terms of high speed, low power, low noise and intrinsic anti-aliasing capability. In this paper, we concentrate on the discrete implementation. Section 2 presents an aperture jitter effect in SDM in terms of SNR. In the last few years different authors derived formulas to quantify the SNR limiting effect of jitter in ADCs. While Walden used a worst case approach, Kobayashi presented an exact formula which allows calculating the SNR in the presence of an aperture jitter.

A precise return-to-zero current steering DAC is presented. This architecture uses a scaled switched-capacitor replica and a comparator to integrate the current over time, resulting in an accurate pulse. Without significant increase in the pulse height, the generated pulse can have its minimal value at the end of the DAC phase, hence minimizing the clock jitter effect. The proposed DAC can be used in continuous-time delta-sigma modulators to achieve high accuracy even in presence of the clock jitter. Simulation results are provided to prove the efficiency of this structure.

Multi-bit continuous time Sigma Delta ($\Sigma\Delta$) modulators are the necessary drivers of modern high speed and low power analog to digital conversion technology. The use of multi-bit quantization in a continuous Time $\Sigma\Delta$ modulator has been limited because nonlinearity in the DAC (Digital to Analog Converter) of a sigma delta modulator translates directly into nonlinearity of the entire modulator, producing a distorted output. Nonlinearity in the DAC modulates the quantization noise into the signal band, thus degrading its performance. It is desired to estimate this non-linearity and apply a correction to nullify its effects. In this paper, a non-invasive background calibration technique is presented for the mismatch estimation and correction of static mismatches in the feedback DAC elements of a continuous time sigma delta modulator. The proposed design can fit into an existing modulator deploying a multi-bit D.AC. It is demonstrated by simulations that the proposed design achieves over 100dB THD performance across 40MHz signal bandwidth for an OSR (Over Sampling Ratio) of 30. The architecture works well even for topologies with achieving very high performance.

To reduce simulation times, continuous time (CT) sigma-delta modulators can be modeled as equivalent discrete time (DT) systems so that DT simulators can be used. This method reviews two popular methods of converting from CT to DT and applies them to a second order CT complex ADC. The ADC being designed is for use with a low IF receiver and achieves 80dB SNDR in simulation.

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a 2-D Markov chain, and the output jitter is smaller than but close to that of a first-order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first-order loop; it is proportional to the clock jitter and inversely proportional to the square root of the stability factor-the ratio of the proportional-path gain to the integral-path gain of the digital loop filter.

This paper covers a general design guidelines, implementation issues as well as performance limitations of a clock-jitter insensitive multibit digital-to-analog converter (DAC) topology for high-performance low-power continuous-time /spl Sigma//spl Delta/ modulators. Since, the considered DAC building block uses a time-variant feedback pulse shape both the clock jitter influence as well as the slew rate and bandwidth requirements of the used amplifiers are reduced so that also the overall power consumption of the modulator is decreased. It will be shown that the proposed concept provides various benefits over the commonly used current-source DACs. Additionally, the influence of a number of circuit non-idealities is analytically determined and verified by behavioural simulations in order to minimize their impact on the modulator performance on the one hand and to optimize the overall power consumption on the other hand. In particular, the effects of clock jitter, random device mismatch, finite switch resistance, circuit noise as well as the limited output impedance is analyzed. Besides, the impact of amplifier confinements like finite DC-gain as well as gain-bandwidth are evaluated.

This paper reports a fourth-order continuous-time (CT) delta-sigma modulator (DSM) that features a single biquad integrator, a passive integrator and an active integrator. A benefit is the low power consumption using only two opamps in comparison to 4 power-hungry opamps in the conventional fourth-order DSM. The proposed CT-DSM employs two Miller compensation opamps to satisfy the gain bandwidth (GBW) requirement and the loop gain requirement. In this design, the GBW is only 1.65 times higher than the sampling frequency and the open loop DC gain is much higher than the oversampling rate. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to complete the CT DSM including the feedback paths. The effective number of bits of the proposed CT-DSM is 14 bits with a peak SNR of 90.5 dB. The proposed design has a maximum bandwidth of 2 MHz with a power consumption less than 3 mW. Thus, it achieves an excellent figure of merit around 175 dB compared to existing state-of-the-art.

Chapter 4 introduces the principle of delta-sigma ADCs. It discussed the switched-capacitor technique together with its advantages. The precision of the transfer function is only dependent on capacitive matching, which is typically 0.1 % accurate. The clock frequency can further vary in a wide range without affecting the stability. This is due as only the sampled charge is transferred to the integrator, which therefore will not saturate when changing the clock frequency. Furthermore, the clock jitter only affects the system noise hardly. The input signal will be sampled at a wrong point of time. However, due to the oversampling, the input frequencies are low anyhow, where noise based on clock jitter can normally be neglected.

This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm2.

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator and low noise amplifier (LNA) with data-weighted average (DWA) technology. A new image-reject low noise amplifier is designed for ECG communication and bio-signal wireless acquisitions. An inter-stage T-structure filter is used in the low noise amplifier design to provide 35-dB image rejection. The DWA technique is used for reducing DAC noise due to component mismatches. Experimental results show the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply, which can be used for electroencephalogram (EEG) or electrocardiogram (ECG) signal acquisition systems by wireless sensor and communication. This provided sensor setup CO2 concentration detecting instruments on chip. Oxygen generator will real time to support when sensor monitor and wireless send bio-signal to doctor or health cloud.

We present a technique to compensate the effects of process variation induced R-C / <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{g}_{\mathrm{m}}-\mathrm{C}$</tex> time-constant (TC) errors in continuous-time (CT) delta-sigma modulators with multibit quantizers. Tunable error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with actively tunable circuit structures, such as the digital-to-analog converters in the feedback paths. This work constitutes a generalization of our previously published TC error compensation technique, which only considered modulators with single-bit quantizers. In the multi-bit case, special attention must be paid to the adjustment of the effective quantizer gain as a function of TC errors on the system and the circuit levels. We derive an active TC tuning scheme for multi-bit CT delta-sigma modulators in cascaded integrator feedback structure. The tuning scheme is applied to a 3-bit modulator circuit implemented in a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.35-\mu \mathrm{m}$</tex> CMOS process. Corner simulations on the transistor level confirm constant nominal performance and stable operation across TC variation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm \mathbf{3 0} \boldsymbol{\%}$</tex>.

This paper presents the system-level design and behavioural implementation of a second-order continuous-time (CT)sigma-delta modulator for high-resolution, low-frequency sensing applications. The modulator architecture is synthesized using the MATLAB Delta-Sigma Toolbox and implemented behaviorally in Cadence Virtuoso using Verilog-A models. A cascade of integrators feed-forward (CIFF) architecture with a 1-bit quantizer and an oversampling ratio (OSR) of 12 is employed to achieve high resolution while maintaining stability. The discrete-time noise transfer function (NTF) is transformed to its continuous-time equivalent using the impulseinvariant transformation with an NRZ feedback DAC pulse. Simulation results demonstrate practical second-order noise shaping. For a 900 mV, 1 Hz sinusoidal input, the modulator achieves an SNR of 86dB, corresponding to an effective number of bits (ENOB) of 14 bits. The influence of the integrator's finite DC gain and limited gainbandwidth product (GBW) on performance is also evaluated. The results validate the proposed modulator architecture for precision low-bandwidth sensing front-end applications.