Continuous-Time Delta-Sigma ADCs

This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM's output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM's quantization noise transfer function; 4) DAC's pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed.

The effect of clock jitter on the dynamic range of discrete-time (DT) and continuous-time (CT) sigma-delta modulators is addressed. It is shown that clock jitter in DT modulators mixes with the input signal, while for CT modulators, the jitter mixes with the out-of-band quantization error and elevates the passband noise. The signal-to-noise ratio of CT modulators is shown to be more susceptible to clock jitter than their DT counterparts. Analytical and simulation results are provided.

The effect of certain fundamental nonidealities on the resolution of a continuous-time (CT) delta sigma modulator are examined in this paper. We start by talking about the equivalence between an ideal CT delta sigma modulator and its discrete-time (DT) counterpart, then consider the effect of quantizer/DAC propagation delay, clock jitter, and the recently-identified phenomenon of signal-dependent jitter on the ideal performance.

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

The past few years has seen a tremendous amount of work being published in the area of continuous-time delta-sigma ADC designs with various compensation techniques to counter its susceptibility to non-idealities like clock jitter and excess loop delay, to name a few. The focus of this paper is the design of a tunable continuous time bandpass delta-sigma modulator that utilizes an excess loop delay compensation technique proposed in [1] to optimize the SNR of the modulator, besides preserving its stability by incorporating a full clock cycle delay. An improved, low noise, compact gyrator-C structure is proposed to obtain a high-Q bandpass filter subsequently used in the design of a second-order bandpass delta-sigma modulator clocked at 400 MHz for direct conversion of narrow band signals around 100 MHz. The proposed structure eliminates the need of a capacitor bank/array for the coarse tuning of the modulator since this structure enables coarse tuning in the range of 80 to 120 MHz and fine tuning of 5 MHz above or below the centre frequency. This modulator has been implemented in AMI 0.5µ CMOS process and achieves an SNR of 46 dB over a bandwidth of 1 MHz, calculated from post-layout simulations. The power consumption of this design is 49 mW at a supply of 3V.

The performance of Continuous Time Delta-Sigma Modulators (CT-AEMs) is limited by clock jitter in the outermost feedback DAC. As one solution, FIR-DACs have been introduced to improve the modulators jitter robustness. In literature, those FIR-DACs have been described with equal coefficients for all taps. This paper investigates the effect of using non-equal symmetric taps on the modulators performance. A comparison between the two FIR filters (equal and non-equal symmetric taps) regarding jitter immunity, sensitivity to coefficient mismatch, complexity of the filters and the required compensation filter are presented. Furthermore, the effect of the FIR filters on the modulators dynamic requirements and its STF are discussed. The paper shows that symmetric non-equal coefficients outperform the equal coefficients configuration in all aspects without sacrificing hardware complexity, resulting in an extension of the modulator's jitter immunity limit and reduction of power consumption.

In a high-speed sampling system, the clock jitter of analog-to-digital converters (ADCs) will greatly affect its sampling accuracy, leading to the reduction of the signal-to-noise ratio (SNR) of the system output. Therefore, it is necessary to compensate the sampling results to reduce the sampling error caused by clock jitter by measuring the distribution sequence of jitter. In this paper, the influence of clock jitter on the ADC sampling process is analyzed, and an ADC clock jitter measurement scheme based on a simple coherent sampling algorithm is investigated. This scheme can accurately measure the distribution sequence of clock jitter, and has the characteristics of low computational complexity and high precision. The simulation results show that this algorithm can accurately measure the clock jitter sequence with root-mean-square (RMS) greater than 5ps when the amplitude noise of the input signal is greater than 35dB, and the relative error is less than 5%.

A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC). In such applications, the frequency multiplication ratio is always larger than 800 and can be up to over 2600. The output pixel clock has to be phase aligned to the HSYNC. Otherwise, the displayed image will become blurry. A fast phase tracking all-digital PLL (ADPLL) for video pixel clock generation in a 65 nm CMOS technology is presented in this paper. In the proposed ADPLL, the digital loop filter eliminates the reference clock jitter effects and then the period jitter of the output pixel clock can be reduced. A time-to-digital converter (TDC) and a delta-sigma modulator (DSM) are used to perform the fast phase tracking, and the tracking jitter is controlled at less than one-third of the output pixel clock period. As compared to prior studies, the proposed ADPLL does not require an extra external oscillator to overcome the reference clock jitter effects. Thus, it has a small chip area and low power consumption, and is well-suited to video pixel clock generation applications in 65 nm CMOS process.

Continuous-time delta-sigma (CT DSM) ADCs offer implicit antialiasing and a resistive input impedance. This allows a dramatic relaxation of the ADC’s antialiasing filter requirement and a drastic simplification of its driver’s design. This has proved transformative in the particular case of integrated narrowband direct conversion receivers (RXs) where, following the mixer, a simple T1A with a firstorder roll-off is sufficient to drive the ADC (Fig. 1). The ADC, however, must be easy to integrate, have no signal transfer function (STF) peaking, and satisfy the stringent requirements of >90dB SFDR with >80dB antialiasing and an NSD <-150dBFS/Hz over lMHz bandwidth with low power dissipation. The resistive feedback DAC (RDAC) has been critical to achieving a low-NSD CT DSM with low power. However, reference-switched RDACs (Fig. 2) suffer from higher sensitivity to reference impedance [1]. The virtual-ground-switched RDAC[I] is less sensitive to this, but sampling of the virtual ground node by the RDAC switches severely degrades the ADC’s antialiasing; e.g., it is only 50dB in [1] [2]. Further, prior RDAC work relies on off-chip references [1] –[4], a major limitation for an ADC that is part of a production-level integrated RX due to associated overheads such as extra 1/O pins and need for external decoupling.

Multirating has been recently proposed to reduce the frequency rate of the first integrator(s) of a single-loop, or the first stage(s) of a cascade, Sigma-Delta modulator (SDM). This is a promising technique for the design of high speed, low-power modulators, as the first integrator (or stage) in the chain primarily determines the performances of the modulator, as well as its power consumption. This paper presents the first implementation of a 2nd-order multirate SDM, showing different circuit solutions. The experimental results obtained with a prototype in a standard 0.6 ?m CMOS technology shows that different clock rates can be selected for each integrator of a SDM.

A precise return-to-zero current steering DAC is presented. This architecture uses a scaled switched-capacitor replica and a comparator to integrate the current over time, resulting in an accurate pulse. Without significant increase in the pulse height, the generated pulse can have its minimal value at the end of the DAC phase, hence minimizing the clock jitter effect. The proposed DAC can be used in continuous-time delta-sigma modulators to achieve high accuracy even in presence of the clock jitter. Simulation results are provided to prove the efficiency of this structure.

Continuous time sigma-delta ADCs usually are designed with noise transfer functions containing conjugate complex zeros to extend the usable bandwidth. Traditionally, these zeros are implemented with a resonance generated by local feedback around two integrators. Recently a loop filter topology with reduced number of opamps based on modified Twin-T single-opamp resonators has been proposed with the aim to reduce power dissipation. In this work, we propose an alternative differential single opamp resonator with cross-coupled feedback, which is more compact, more power efficient, more robust to parasitics and more linear than the Twin-T based single-opamp resonators.

This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.

Even though highly selective ion pumps are found in the membrane of every living cell, artificial ion selective separation is a longstanding unmet challenge in science and engineering. The development of a membrane-based ion separation technology can drive a dramatic progress in a wide range of applications such as: water treatment, bio-medical devices, extraction of precious metals from sea water, chemical sensors, solar fuels and more. In this contribution we report on the experimental demonstration of ion pumps based on an electronic flashing ratchet mechanism and their theoretical ion sorting performance.Electronic flashing ratchets are devices that utilize a temporal modulation of a spatially asymmetric electric field to drive steady state current. Like peristaltic pumps, where the pump mechanism is not in direct contact with the pumped fluid, electronic ratchets induce a net current with no direct charge transport between the power source and the pumped charge carriers. Thus, electronic ratchets can be used to pump ions in steady state with no electrochemical reactions between the power source and the pumped ions resulting in an 'all-electric' ion pump.Ratchet-based ion pumps (RBIPs) were fabricated by coating the two surfaces of nano-porous alumina wafers with metal, thus forming nano-porous capacitor-like devices. The electric field within the nano-pores is modulated by oscillating the capacitor voltage. Thus, when immersed in a solution, ions within the pores experience a modulating electric field resulting in ratchet-based ion pumping. The RBIPs performance was studied for various input signals, geometries, and solutions. RBIPs were shown to drive ionic current densities of several uA/cm^2 even when opposed by an electrostatic force. A significant ratchet action was observed with input signal amplitudes as low as 0.1V thus demonstrating that RBIPs can drive an ionic current with no associated redox reactions.An important hallmark of ratchets is the ability to invert the direction of particle flow with a change in the input signal frequency. The stopping frequency, which is the frequency at which the particle flux changes its direction, is determined by the potential distribution and particles transport properties. As a result, for a given ratchet, there can be a frequency at which particles with the same charge, but different diffusion coefficients, are transported in opposite directions. This concept, that was never applied to ion separations, can enable the extraction of ions with extremely low relative concentrations if their diffusion coefficient is even slightly different from the diffusion coefficient of other ions in the solution. We show by simulation, that for the prevalent ions in water, ions with a relative diffusion coefficient difference as small as 1% can be driven to opposite directions with a velocity difference as high as 1.2 mm/s. Since the direction of ion transport is determined by the input signal frequency, the sorting properties can be tuned in real time providing a simple fit-to-purpose solution for a variety of ion separations applications. Figure 1

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications