A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding

The fact that VCO-ADCs produce noise-shaped quantization noise suggests that a link between frequency modulation and Sigma-Delta modulation should exist. The connection between a VCO-ADC and a first-order Sigma-Delta modulator has been already explained using Pulse Frequency Modulation. In this article, we attempt to extend this explanation to a generic Sigma-Delta modulator. We show that the link between Sigma-Delta modulation and Pulse Frequency Modulation relies in a sampling invariance property that defines the equivalence between both entities. This equivalence property, allows to go beyond the white quantization noise model of a Sigma-Delta modulator, revealing the origin of some nonlinear phenomena. We first predict spurious tones which cannot be explained by circuit non linearity. Multi-bit and single-bit modulators are shown to belong to a same generic class of systems. Finally, quantizer overload is analyzed using our model. The results are applied to Continuous-Time Sigma-Delta modulators of orders one, two and three and then extended to a generic case.

Multi-bit continuous time Sigma Delta ($\Sigma\Delta$) modulators are the necessary drivers of modern high speed and low power analog to digital conversion technology. The use of multi-bit quantization in a continuous Time $\Sigma\Delta$ modulator has been limited because nonlinearity in the DAC (Digital to Analog Converter) of a sigma delta modulator translates directly into nonlinearity of the entire modulator, producing a distorted output. Nonlinearity in the DAC modulates the quantization noise into the signal band, thus degrading its performance. It is desired to estimate this non-linearity and apply a correction to nullify its effects. In this paper, a non-invasive background calibration technique is presented for the mismatch estimation and correction of static mismatches in the feedback DAC elements of a continuous time sigma delta modulator. The proposed design can fit into an existing modulator deploying a multi-bit D.AC. It is demonstrated by simulations that the proposed design achieves over 100dB THD performance across 40MHz signal bandwidth for an OSR (Over Sampling Ratio) of 30. The architecture works well even for topologies with achieving very high performance.

The effect of certain fundamental nonidealities on the resolution of a continuous-time (CT) delta sigma modulator are examined in this paper. We start by talking about the equivalence between an ideal CT delta sigma modulator and its discrete-time (DT) counterpart, then consider the effect of quantizer/DAC propagation delay, clock jitter, and the recently-identified phenomenon of signal-dependent jitter on the ideal performance.

This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM's output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM's quantization noise transfer function; 4) DAC's pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed.

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

This brief presents a power reduction technique for continuous time sigma–delta modulators (CTSDMs). The approach consists of two elements. First, a passive low-pass filter is added in front of the modulator’s loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low-pass filter also changes the modulator’s loop gain, and hence affects the noise transfer functions (NTFs) and signal transfer functions (STFs), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs, where the amount of high-frequency components in the loop is excessive. To showcase the technique, a self-oscillating sigma–delta modulator (which is a dedicated type of one-bit CTSDM) was implemented in a 65-nm CMOS process. It achieves a peak signal to noise and distortion ratio of 63 dB over a 20-MHz bandwidth at a power consumption of 1.7 mW while occupying a very small chip area of only 0.009 mm2.

In this work, a method for the concurrent estimation of nonidealities in continuous-time sigma-delta modulators is presented. Several nonidealities can degrade the performance of a sigma-delta modulator, even up to instability of the entire circuit. However, if these nonidealities are known, it is possible to correct for most of them - either in the analog or digital domain. In the past, many techniques for corrections of errors in sigma-delta modulators have been presented. Although these works show good results, most are only able to work on a single or few nonidealities simultaneously. In this paper, a feasible approach for estimating several nonidealities in a joint fashion has been applied to estimate some of the most prominent errors in a continuous-time sigma-delta modulator.

The envelope pulse-width modulation (EPWM) transmitter has been studied to address the power efficiency issue on the linear amplification of OFDM signals. However, the delta- sigma (Delta-Sigma) modulator in the EPWM transmitter generates quantization noise that degrades signal quality. In this paper, OFDM in-band noise characteristics of EPWM transmitters are analyzed for first and second order Delta-Sigma modulators. Distortion noise power due to envelope clipping of OFDM signals is also analyzed. The combined effects of noise and distortion on the error vector magnitude (EVM) and adjacent channel leakage power ratio (ACLR) are examined. Simulations to validate the total performance were performed using the IEEE 802.11a OFDM signal. Results showed good agreement with analytical results considering a linear-approximation gain for the 1-bit quantizer in Delta-Sigma modulators. The first order EPWM transmitter provides slightly better EVM and ACLR values than second order EPWM transmitters, since the effective quantizer gain of second order Delta-Sigma modulators is smaller, that limits the noise- shaping capability of Delta-Sigma modulators. A 0.1% clipping probability for a first order EPWM transmitter with an oversampling ratio of 32 and a three-pole Butterworth bandpass filter gives an EVM of 1.8% and ACLR of-37.9 dB.

This paper reports a fourth-order continuous-time (CT) delta-sigma modulator (DSM) that features a single biquad integrator, a passive integrator and an active integrator. A benefit is the low power consumption using only two opamps in comparison to 4 power-hungry opamps in the conventional fourth-order DSM. The proposed CT-DSM employs two Miller compensation opamps to satisfy the gain bandwidth (GBW) requirement and the loop gain requirement. In this design, the GBW is only 1.65 times higher than the sampling frequency and the open loop DC gain is much higher than the oversampling rate. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to complete the CT DSM including the feedback paths. The effective number of bits of the proposed CT-DSM is 14 bits with a peak SNR of 90.5 dB. The proposed design has a maximum bandwidth of 2 MHz with a power consumption less than 3 mW. Thus, it achieves an excellent figure of merit around 175 dB compared to existing state-of-the-art.

We designed and simulating delta sigma ADC for the ECG signal processing in order to achieve high signal to quantization noise ratio by using over sampling concept and low resolution ADC and DAC. The Proposed work will contain system level modeling, simulation and implementation of blocks used in delta sigma ADC. It is compared with ideal blocks done in simulation. The system level design of third order feedforward (CIFF) structure of continuous time delta sigma modulator is proposed employed in ADC in order to reduce power consumption. The efficiency of the proposed ADC is measured in terms of noise spectrum, maximum stable input amplitude range, simulation performance and accuracy. The targeted signal to noise ratio (SNR) is more than 90 dB with resolution more than 12 bit.

This paper demonstrates the effectiveness and robustness of amplifier finite gain bandwidth compensation within a wideband third order continuous time delta sigma modulator and the effects of process, mismatch and temperature on modulator stability. In many state of the art designs, GBW is kept safely above the sampling frequency of the modulator, which suffers a power penalty especially for high-speed designs. While gain errors and phase shifts in the loop filter due to finite GBW can be compensated for, its robustness is often questionable, especially if an additional excess loop delay is concerned. The robustness of such a compensation is analyzed for an exemplary CT DSM with an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> of 500MHz which has been designed in a 1.2V 90nm TSMC CMOS process. Therefore, the amplifiers are compensated for finite GBW values of 500 MHz, 300MHz and 600 MHz, and all three parasitic extracted amplifiers are analyzed over PVT. The simulated modulator performance of 72 dB SNDR over a 25MHz bandwidth is only degraded by 2 dB over corner simulations. In comparison to Monte Carlo analysis of all amplifiers, this reveals a modulator robustness to amplifier finite GBW as much as ±35% over process and mismatch, which emphasizes the feasibility of the approach.

This paper presents a review of high speed continuous time delta sigma modulators (CTDSM) designed for wideband applications. It analyzes different trade-offs involved in its design and choices available at architectural level suggesting the recipe for optimized design of wideband CTDSMs. It also discusses various design techniques used in the design of wideband CTDSMs and compares the performance of state-of-the-art wideband CTDSMs. This paper can serve as a starting point for the design of a low power wideband CTDSM.

This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm2.

A methodology for the simulation of bandpass continuous time sigma-delta (SigmaDelta) modulators is presented in this paper. This method permits the simulation of SigmaDelta modulators employing continuous-time filters using a fixed-step algorithm. The method is based on the discretization of a continuous-time model and the use of a discrete simulator, which is more efficient than an analog simulator. This transformation is exact in term of noise transfer function and asymptotically exact in term of signal transfer function (the signal transfer function of the model rapidly tends to the continuous time model transfer function when the number of steps increases).

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications